mb/google/brask/var/lisbon: Update gpio table
Based on latest schematic to update the gpio table. BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I531f9ca9f6902d3318e99dadb58a811a4686a6e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Kevin Chiu
Felix Held
parent
acd3788bb8
commit
1be4bbc57a
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# SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += gpio.c
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romstage-y += gpio.c
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ramstage-y += gpio.c
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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#include <soc/gpio.h>
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/* Pad configuration in ramstage */
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static const struct pad_config override_gpio_table[] = {
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/* A14 : USB_OC1# ==> NC */
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PAD_NC_LOCK(GPP_A14, NONE, LOCK_CONFIG),
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/* A15 : USB_OC2# ==> NC */
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PAD_NC_LOCK(GPP_A15, NONE, LOCK_CONFIG),
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/* A18 : DDSP_HPDB ==> HDMIB_HPD */
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PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
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/* A19 : DDSP_HPD1 ==> NC */
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PAD_NC_LOCK(GPP_A19, NONE, LOCK_CONFIG),
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/* A20 : DDSP_HPD2 ==> NC */
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PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG),
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/* A21 : DDPC_CTRCLK ==> EN_PP3300_EMMC */
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PAD_CFG_GPO(GPP_A21, 1, DEEP),
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/* A22 : DDPC_CTRLDATA ==> NC */
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PAD_NC_LOCK(GPP_A22, NONE, LOCK_CONFIG),
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/* B2 : VRALERT# ==> M2_SSD_PLA_L */
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PAD_NC(GPP_B2, NONE),
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/* B3 : PROC_GP2 ==> EMMC_PERST_L */
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PAD_CFG_GPO(GPP_B3, 1, DEEP),
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/* B7 : ISH_12C1_SDA ==> PCH_I2C_MISCB_SDA */
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PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
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/* B8 : ISH_I2C1_SCL ==> PCH_I2C_MISCB_SCL */
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PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
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/* D0 : ISH_GP0 ==> NC */
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PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG),
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/* D1 : ISH_GP1 ==> NC */
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PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG),
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/* D2 : ISH_GP2 ==> NC */
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PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG),
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/* D3 : ISH_GP3 ==> NC */
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PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
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/* D9 : ISH_SPI_CS# ==> NC */
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PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
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/* D10 : ISH_SPI_CLK ==> GPI */
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PAD_CFG_GPI_LOCK(GPP_D10, NONE, LOCK_CONFIG),
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/* D17 : UART1_RXD ==> NC */
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PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG),
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/* E4 : SATA_DEVSLP0 ==> NC */
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PAD_NC(GPP_E4, NONE),
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/* E5 : SATA_DEVSLP1 ==> USB_A0_RT_RST_ODL */
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PAD_CFG_GPO(GPP_E5, 1, DEEP),
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/* E14 : DDSP_HPDA ==> HDMIA_HPD */
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PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
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/* E18 : DDP1_CTRLCLK ==> NC */
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PAD_NC(GPP_E18, NONE),
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/* E20 : DDP2_CTRLCLK ==> DDIA_HDMI_CTRLCLK */
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PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
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/* E21 : DDP2_CTRLDATA ==> DDIA_HDMI_CTRLDATA */
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PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
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/* F11 : THC1_SPI2_CLK ==> NC */
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PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
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/* F12 : GSXDOUT ==> NC */
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PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
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/* F13 : GSXDOUT ==> NC */
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PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
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/* F15 : GSXSRESET# ==> NC */
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PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
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/* F16 : GSXCLK ==> NC */
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PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
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/* H19 : SRCCLKREQ4# ==> CLKREQ_4 */
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PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
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/* H21 : IMGCLKOUT2 ==> EMMC_PE_WAKE_ODL */
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PAD_CFG_GPO(GPP_H21, 1, DEEP),
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/* R4 : HDA_RST# ==> NC */
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PAD_NC(GPP_R4, NONE),
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/* R5 : HDA_SDI1 ==> NC */
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PAD_NC(GPP_R5, NONE),
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/* R6 : I2S2_TXD ==> NC */
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PAD_NC(GPP_R6, NONE),
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/* R7 : I2S2_RXD ==> NC */
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PAD_NC(GPP_R7, NONE),
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};
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
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/* A21 : DDPC_CTRCLK ==> EN_PP3300_EMMC */
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PAD_CFG_GPO(GPP_A21, 1, DEEP),
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/* B3 : PROC_GP2 ==> EMMC_PERST_L */
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PAD_CFG_GPO(GPP_B3, 0, DEEP),
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/* B4 : PROC_GP3 ==> SSD_PERST_L */
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PAD_CFG_GPO(GPP_B4, 0, DEEP),
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/* E15 : RSVD_TP ==> PCH_WP_OD */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
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/* F14 : GSXDIN ==> EN_PP3300_SSD */
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PAD_CFG_GPO(GPP_F14, 1, DEEP),
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/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
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PAD_CFG_GPI(GPP_F18, NONE, DEEP),
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/* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */
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PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
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/* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */
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PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
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/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
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PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
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/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
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PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
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/* H13 : I2C7_SCL ==> EN_PP3300_SD */
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PAD_CFG_GPO(GPP_H13, 1, DEEP),
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/* CPU PCIe VGPIO for PEG60 */
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
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};
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static const struct pad_config romstage_gpio_table[] = {
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/* B3 : PROC_GP2 ==> EMMC_PERST_L */
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PAD_CFG_GPO(GPP_B3, 1, DEEP),
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/* B4 : PROC_GP3 ==> SSD_PERST_L */
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PAD_CFG_GPO(GPP_B4, 1, DEEP),
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};
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const struct pad_config *variant_gpio_override_table(size_t *num)
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{
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*num = ARRAY_SIZE(override_gpio_table);
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return override_gpio_table;
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}
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const struct pad_config *variant_early_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(early_gpio_table);
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return early_gpio_table;
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}
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const struct pad_config *variant_romstage_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(romstage_gpio_table);
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return romstage_gpio_table;
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}
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