Gale board: Move TPM setup function to verstage.c

TPM should be only be reset once in verstage.

BUG=chrome-os-partner:51096
TEST=Depthcharge no longer shows TPM error.
BRANCH=None

Original-Signed-off-by: Kan Yan <kyan@google.com>
Original-Commit-Id: 911bdaa83a05fa5c8ea82656be0ddc74e19064c3
Original-Change-Id: I52ee6f2c2953e95d617d16f75c8831ecf4f014f9
Original-Reviewed-on: https://chromium-review.googlesource.com/343537
Original-Commit-Ready: Kan Yan <kyan@google.com>
Original-Tested-by: Kan Yan <kyan@google.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I8047b7ba44c604d97a662dbf400efc9eea2c7719
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14845
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>

src/mainboard/google/gale/Makefile.inc

@@ -24,6 +24,7 @@ verstage-y += chromeos.c
 verstage-y += blsp.c
 verstage-y += memlayout.ld
 verstage-y += reset.c
+verstage-y += verstage.c
 
 romstage-y += romstage.c
 romstage-y += cdp.c

src/mainboard/google/gale/mainboard.c

@@ -37,39 +37,6 @@ static void setup_usb(void)
 	setup_usb_host1();
 }
 
-#define TPM_RESET_GPIO		19
-void ipq_setup_tpm(void)
-{
-	if (!IS_ENABLED(CONFIG_I2C_TPM))
-		return;
-
-	gpio_tlmm_config_set(TPM_RESET_GPIO, FUNC_SEL_GPIO,
-			     GPIO_PULL_UP, GPIO_6MA, 1);
-	gpio_set(TPM_RESET_GPIO, 0);
-	udelay(100);
-	gpio_set(TPM_RESET_GPIO, 1);
-
-	/*
-	 * ----- Per the SLB 9615XQ1.2 spec -----
-	 *
-	 * 4.7.1 Reset Timing
-	 *
-	 * The TPM_ACCESS_x.tpmEstablishment bit has the correct value
-	 * and the TPM_ACCESS_x.tpmRegValidSts bit is typically set
-	 * within 8ms after RESET# is deasserted.
-	 *
-	 * The TPM is ready to receive a command after less than 30 ms.
-	 *
-	 * --------------------------------------
-	 *
-	 * I'm assuming this means "wait for 30ms"
-	 *
-	 * If we don't wait here, subsequent QUP I2C accesses
-	 * to the TPM either fail or timeout.
-	 */
-	mdelay(30);
-}
-
 static void mainboard_init(device_t dev)
 {
 	/* disable mmu and d-cache before setting up secure world.*/
@@ -78,7 +45,6 @@ static void mainboard_init(device_t dev)
 	/* Setup mmu and d-cache again as non secure entries. */
 	setup_mmu(DRAM_INITIALIZED);
 	setup_usb();
-	ipq_setup_tpm();
 
 	if (IS_ENABLED(CONFIG_CHROMEOS)) {
 		/* Copy WIFI calibration data into CBMEM. */

src/mainboard/google/gale/verstage.c

@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <delay.h>
+#include <gpio.h>
+#include <soc/verstage.h>
+
+
+#define TPM_RESET_GPIO		19
+
+static void ipq_setup_tpm(void)
+{
+
+#ifdef CONFIG_I2C_TPM
+	gpio_tlmm_config_set(TPM_RESET_GPIO, FUNC_SEL_GPIO,
+			     GPIO_PULL_UP, GPIO_6MA, 1);
+	gpio_set(TPM_RESET_GPIO, 0);
+	udelay(100);
+	gpio_set(TPM_RESET_GPIO, 1);
+
+	/*
+	 * ----- Per the SLB 9615XQ1.2 spec -----
+	 *
+	 * 4.7.1 Reset Timing
+	 *
+	 * The TPM_ACCESS_x.tpmEstablishment bit has the correct value
+	 * and the TPM_ACCESS_x.tpmRegValidSts bit is typically set
+	 * within 8ms after RESET# is deasserted.
+	 *
+	 * The TPM is ready to receive a command after less than 30 ms.
+	 *
+	 * --------------------------------------
+	 *
+	 * I'm assuming this means "wait for 30ms"
+	 *
+	 * If we don't wait here, subsequent QUP I2C accesses
+	 * to the TPM either fail or timeout.
+	 */
+	mdelay(30);
+
+#endif /* CONFIG_I2C_TPM */
+}
+
+void verstage_mainboard_init(void)
+{
+	ipq_setup_tpm();
+}

src/soc/qualcomm/ipq40xx/include/soc/gpio.h

@@ -114,6 +114,4 @@ static inline void gpio_tlmm_config(unsigned int gpio, unsigned int func,
 	gpio_tlmm_config_set(gpio, func, pull, drvstr, enable);
 }
 
-void ipq_setup_tpm(void);
-
 #endif // __SOC_QUALCOMM_IPQ40XX_GPIO_H_

src/soc/qualcomm/ipq40xx/include/soc/verstage.h

@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_QUALCOMM_IPQ40XX_INCLUDE_SOC_VERSTAGE_H__
+#define __SOC_QUALCOMM_IPQ40XX_INCLUDE_SOC_VERSTAGE_H__
+
+#include <vendorcode/google/chromeos/chromeos.h>
+
+#endif /*  __SOC_QUALCOMM_IPQ40XX_INCLUDE_SOC_VERSTAGE_H__ */