arch/x86: Use a common timestamp.inc with romcc bootblocks
The same file was replicated three times for certain soc/intel bootblocks, yet there are no indications or need to do chipset-specific initialisation. There is no harm in storing the TSC values in MMX registers even when they would not be used. Change-Id: Iec6fa0889f5887effca1d99ef830d383fb733648 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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@ -19,7 +19,7 @@
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* - reset16.inc: the reset vector
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* - reset16.inc: the reset vector
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* - entry16.inc: protected mode setup
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* - entry16.inc: protected mode setup
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* - entry32.inc: segment descriptor setup
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* - entry32.inc: segment descriptor setup
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* - CONFIG_CHIPSET_BOOTBLOCK_INCLUDE: chipset-specific initialization
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* - timestamp.inc: store TSC in MMX registers
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* - generated/bootblock.inc: ROMCC part of the bootblock
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* - generated/bootblock.inc: ROMCC part of the bootblock
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*
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*
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* This is used on platforms which do not select C_ENVIRONMENT_BOOTBLOCK, and it
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* This is used on platforms which do not select C_ENVIRONMENT_BOOTBLOCK, and it
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@ -35,9 +35,7 @@
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#include <cpu/x86/16bit/reset16.inc>
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#include <cpu/x86/16bit/reset16.inc>
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#include <cpu/x86/32bit/entry32.inc>
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#include <cpu/x86/32bit/entry32.inc>
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#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
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#include <arch/x86/timestamp.inc>
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#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
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#endif
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#if IS_ENABLED(CONFIG_SSE)
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#if IS_ENABLED(CONFIG_SSE)
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#include <cpu/x86/sse_enable.inc>
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#include <cpu/x86/sse_enable.inc>
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@ -166,8 +166,4 @@ config REFCODE_BLOB_FILE
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endif # HAVE_REFCODE_BLOB
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endif # HAVE_REFCODE_BLOB
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config CHIPSET_BOOTBLOCK_INCLUDE
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string
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default "soc/intel/baytrail/bootblock/timestamp.inc"
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endif
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endif
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@ -123,10 +123,6 @@ config IED_REGION_SIZE
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hex
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hex
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default 0x400000
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default 0x400000
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config CHIPSET_BOOTBLOCK_INCLUDE
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string
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default "soc/intel/braswell/bootblock/timestamp.inc"
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config DISABLE_HPET
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config DISABLE_HPET
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bool "Disable the HPET device"
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bool "Disable the HPET device"
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default n
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default n
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@ -1,33 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* Store the initial timestamp for booting in mmx registers. This works
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* because the bootblock isn't being compiled with MMX support so mm0 and
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* mm1 will be preserved into romstage.
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*/
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.code32
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.global stash_timestamp
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stash_timestamp:
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/* Save the BIST value */
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movl %eax, %ebp
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finit
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rdtsc
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movd %eax, %mm0
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movd %edx, %mm1
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/* Restore the BIST value to %eax */
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movl %ebp, %eax
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@ -204,8 +204,4 @@ config REFCODE_BLOB_FILE
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endif # HAVE_REFCODE_BLOB
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endif # HAVE_REFCODE_BLOB
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config CHIPSET_BOOTBLOCK_INCLUDE
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string
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default "soc/intel/broadwell/bootblock/timestamp.inc"
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endif
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endif
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@ -1,33 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* Store the initial timestamp for booting in mmx registers. This works
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* because the bootblock isn't being compiled with MMX support so mm0 and
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* mm1 will be preserved into romstage.
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*/
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.code32
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.global stash_timestamp
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stash_timestamp:
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/* Save the BIST value */
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movl %eax, %ebp
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finit
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rdtsc
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movd %eax, %mm0
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movd %edx, %mm1
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/* Restore the BIST value to %eax */
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movl %ebp, %eax
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