soc/intel/cannonlake: rename "RSVD" GPIOs to their correct names
The names of the GPIO_RSVD_* are documented in the PCH EDS, in Linux (linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places. Also, see soc/intel/tigerlake for reference. Change-Id: I59df09c8fd464e75f918455aa1972765abc51459 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Michael Niewöhner
parent
748bfac734
commit
1c2b1b977a
6 changed files with 130 additions and 130 deletions
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@ -61,7 +61,7 @@ Device (GPIO)
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Method (GADD, 1, NotSerialized)
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{
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/* GPIO Community 0 */
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If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPIO_RSVD_11)))
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If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, SPI0_CLK_LOOPBK)))
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{
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Store (PID_GPIOCOM0, Local0)
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Subtract (Arg0, GPP_A0, Local1)
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@ -79,13 +79,13 @@ Method (GADD, 1, NotSerialized)
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Subtract (Arg0, GPD0, Local1)
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}
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/* GPIO Community 3 */
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If (LAnd (LGreaterEqual (Arg0, HDA_BCLK), LLessEqual (Arg0, GPIO_RSVD_38)))
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If (LAnd (LGreaterEqual (Arg0, HDA_BCLK), LLessEqual (Arg0, TRIGGER_OUT)))
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{
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Store (PID_GPIOCOM3, Local0)
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Subtract (Arg0, HDA_BCLK, Local1)
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}
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/* GPIO Community 04*/
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If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPIO_RSVD_27)))
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/* GPIO Community 4*/
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If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, CL_RST_B)))
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{
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Store (PID_GPIOCOM4, Local0)
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Subtract (Arg0, GPP_C0, Local1)
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@ -67,25 +67,25 @@ Device (GPIO)
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Method (GADD, 1, NotSerialized)
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{
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/* GPIO Community 0 */
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If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_B23)))
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If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GSPI1_CLK_LOOPBK)))
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{
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Store (PID_GPIOCOM0, Local0)
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Subtract (Arg0, GPP_A0, Local1)
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}
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/* GPIO Community 1 */
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If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_G7)))
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If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, vSSP2_RXD)))
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{
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Store (PID_GPIOCOM1, Local0)
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Subtract (Arg0, GPP_C0, Local1)
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}
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/* GPIO Community 3*/
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If (LAnd (LGreaterEqual (Arg0, GPP_K0), LLessEqual (Arg0, GPP_F23)))
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If (LAnd (LGreaterEqual (Arg0, GPP_K0), LLessEqual (Arg0, SPI0_CLK_LOOPBK)))
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{
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Store (PID_GPIOCOM3, Local0)
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Subtract (Arg0, GPP_K0, Local1)
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}
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/* GPIO Community 4*/
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If (LAnd (LGreaterEqual (Arg0, GPP_I0), LLessEqual (Arg0, GPP_J11)))
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If (LAnd (LGreaterEqual (Arg0, HDACPU_SDI), LLessEqual (Arg0, GPP_J11)))
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{
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Store (PID_GPIOCOM4, Local0)
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Subtract (Arg0, GPP_I0, Local1)
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@ -32,14 +32,14 @@ static const struct reset_mapping rst_map_com0[] = {
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* linux/drivers/pinctrl/intel/pinctrl-cannonlake.c
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*/
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static const struct pad_group cnl_community0_groups[] = {
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INTEL_GPP_BASE(GPP_A0, GPP_A0, GPIO_RSVD_0, 0), /* GPP_A */
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INTEL_GPP_BASE(GPP_A0, GPP_B0, GPIO_RSVD_2, 32), /* GPP_B */
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INTEL_GPP_BASE(GPP_A0, GPP_A0, ESPI_CLK_LOOPBK, 0), /* GPP_A */
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INTEL_GPP_BASE(GPP_A0, GPP_B0, GSPI1_CLK_LOOPBK, 32), /* GPP_B */
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INTEL_GPP_BASE(GPP_A0, GPP_G0, GPP_G7, 64), /* GPP_G */
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INTEL_GPP(GPP_A0, GPIO_RSVD_3, GPIO_RSVD_11), /* SPI */
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INTEL_GPP(GPP_A0, SPI0_IO_2, SPI0_CLK_LOOPBK), /* SPI */
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};
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static const struct pad_group cnl_community1_groups[] = {
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INTEL_GPP_BASE(GPP_D0, GPP_D0, GPIO_RSVD_12, 96), /* GPP_D */
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INTEL_GPP_BASE(GPP_D0, GPP_D0, GSPI2_CLK_LOOPBK, 96), /* GPP_D */
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INTEL_GPP_BASE(GPP_D0, GPP_F0, GPP_F23, 128), /* GPP_F */
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INTEL_GPP_BASE(GPP_D0, GPP_H0, GPP_H23, 160), /* GPP_H */
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INTEL_GPP_BASE(GPP_D0, CNV_BTEN, vSD3_CD_B, 192), /* VGPIO */
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@ -52,15 +52,15 @@ static const struct pad_group cnl_community2_groups[] = {
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/* This community is not visible to the OS */
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static const struct pad_group cnl_community3_groups[] = {
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INTEL_GPP(HDA_BCLK, HDA_BCLK, SSP1_TXD), /* AZA */
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INTEL_GPP(HDA_BCLK, GPIO_RSVD_28, GPIO_RSVD_38), /* CPU */
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INTEL_GPP(HDA_BCLK, HDA_BCLK, I2S1_TXD), /* AZA */
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INTEL_GPP(HDA_BCLK, HDACPU_SDI, TRIGGER_OUT), /* CPU */
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};
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static const struct pad_group cnl_community4_groups[] = {
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INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 256), /* GPP_C */
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INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E23, 288), /* GPP_E */
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INTEL_GPP(GPP_C0, GPIO_RSVD_13, GPIO_RSVD_21), /* JTAG */
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INTEL_GPP(GPP_C0, GPIO_RSVD_22, GPIO_RSVD_27), /* HVMOS */
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INTEL_GPP(GPP_C0, PCH_TDO, ITP_PMODE), /* JTAG */
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INTEL_GPP(GPP_C0, EDP_BKLTEN, CL_RST_B), /* HVMOS */
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};
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static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = {
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@ -68,7 +68,7 @@ static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = {
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[COMM_0] = {
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.port = PID_GPIOCOM0,
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.first_pad = GPP_A0,
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.last_pad = GPIO_RSVD_11,
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.last_pad = SPI0_CLK_LOOPBK,
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.num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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@ -128,7 +128,7 @@ static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = {
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[COMM_3] = {
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.port = PID_GPIOCOM3,
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.first_pad = HDA_BCLK,
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.last_pad = GPIO_RSVD_38,
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.last_pad = TRIGGER_OUT,
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.num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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@ -148,7 +148,7 @@ static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = {
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[COMM_4] = {
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.port = PID_GPIOCOM4,
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.first_pad = GPP_C0,
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.last_pad = GPIO_RSVD_27,
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.last_pad = CL_RST_B,
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.num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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@ -32,15 +32,15 @@ static const struct reset_mapping rst_map_com0[] = {
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* linux/drivers/pinctrl/intel/pinctrl-cannonlake.c
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*/
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static const struct pad_group cnl_community0_groups[] = {
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INTEL_GPP_BASE(GPP_A0, GPP_A0, GPIO_RSVD_0, 0), /* GPP_A */
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INTEL_GPP_BASE(GPP_A0, GPP_B0, GPIO_RSVD_2, 32), /* GPP_B */
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INTEL_GPP_BASE(GPP_A0, GPP_A0, ESPI_CLK_LOOPBK, 0), /* GPP_A */
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INTEL_GPP_BASE(GPP_A0, GPP_B0, GSPI1_CLK_LOOPBK, 32), /* GPP_B */
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};
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static const struct pad_group cnl_community1_groups[] = {
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INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 64), /* GPP_C */
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INTEL_GPP_BASE(GPP_C0, GPP_D0, GPP_D23, 96), /* GPP_D */
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INTEL_GPP_BASE(GPP_C0, GPP_G0, GPP_G7, 128), /* GPP_G */
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INTEL_GPP(GPP_C0, GPIO_RSVD_3, GPIO_RSVD_10), /* AZA */
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INTEL_GPP(GPP_C0, HDA_BCLK, I2S1_TXD), /* AZA */
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INTEL_GPP_BASE(GPP_C0, CNV_BTEN, vISH_UART1_RTS_B, 160),/* VGPIO_0 */
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INTEL_GPP(GPP_C0, vCNV_BT_I2S_BCLK, vSSP2_RXD), /* VGPIO_1 */
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};
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@ -55,14 +55,14 @@ static const struct pad_group cnl_community3_groups[] = {
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INTEL_GPP_BASE(GPP_K0, GPP_H0, GPP_H23, 224), /* GPP_H */
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INTEL_GPP_BASE(GPP_K0, GPP_E0, GPP_E12, 256), /* GPP_E */
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INTEL_GPP_BASE(GPP_K0, GPP_F0, GPP_F23, 288), /* GPP_F */
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INTEL_GPP(GPP_K0, GPIO_RSVD_11, GPIO_RSVD_19), /* SPI */
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INTEL_GPP(GPP_K0, SPI0_IO_2, SPI0_CLK_LOOPBK), /* SPI */
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};
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static const struct pad_group cnl_community4_groups[] = {
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INTEL_GPP(GPIO_RSVD_20, GPIO_RSVD_20, GPIO_RSVD_30), /* CPU */
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INTEL_GPP(GPIO_RSVD_20, GPIO_RSVD_31, GPIO_RSVD_39), /* JTAG */
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INTEL_GPP_BASE(GPIO_RSVD_20, GPP_I0, GPP_I14, 320), /* GPP_I */
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INTEL_GPP_BASE(GPIO_RSVD_20, GPP_J0, GPP_J11, 352), /* GPP_J */
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INTEL_GPP(HDACPU_SDI, HDACPU_SDI, TRIGGER_OUT), /* CPU */
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INTEL_GPP(HDACPU_SDI, PCH_TDO, ITP_PMODE), /* JTAG */
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INTEL_GPP_BASE(HDACPU_SDI, GPP_I0, GPP_I14, 320), /* GPP_I */
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INTEL_GPP_BASE(HDACPU_SDI, GPP_J0, GPP_J11, 352), /* GPP_J */
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};
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static const struct pad_community cnl_communities[] = {
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@ -70,7 +70,7 @@ static const struct pad_community cnl_communities[] = {
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[COMM_0] = {
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.port = PID_GPIOCOM0,
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.first_pad = GPP_A0,
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.last_pad = GPIO_RSVD_2,
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.last_pad = GSPI1_CLK_LOOPBK,
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.num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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@ -130,7 +130,7 @@ static const struct pad_community cnl_communities[] = {
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[COMM_3] = {
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.port = PID_GPIOCOM3,
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.first_pad = GPP_K0,
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.last_pad = GPIO_RSVD_19,
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.last_pad = SPI0_CLK_LOOPBK,
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.num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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@ -149,7 +149,7 @@ static const struct pad_community cnl_communities[] = {
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/* GPP I, J */
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[COMM_4] = {
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.port = PID_GPIOCOM4,
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.first_pad = GPIO_RSVD_20,
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.first_pad = HDACPU_SDI,
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.last_pad = GPP_J11,
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.num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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@ -57,7 +57,7 @@
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#define GPP_A21 21
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#define GPP_A22 22
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#define GPP_A23 23
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#define GPIO_RSVD_0 24
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#define ESPI_CLK_LOOPBK 24
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/* Group B */
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#define GPP_B0 25
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#define GPP_B1 26
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@ -83,8 +83,8 @@
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#define GPP_B21 46
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#define GPP_B22 47
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#define GPP_B23 48
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#define GPIO_RSVD_1 49
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#define GPIO_RSVD_2 50
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#define GSPI0_CLK_LOOPBK 49
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#define GSPI1_CLK_LOOPBK 50
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/* Group G */
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#define GPP_G0 51
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#define GPP_G1 52
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@ -95,17 +95,17 @@
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#define GPP_G6 57
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#define GPP_G7 58
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/* Group SPI */
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#define GPIO_RSVD_3 59
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#define GPIO_RSVD_4 60
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#define GPIO_RSVD_5 61
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#define GPIO_RSVD_6 62
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#define GPIO_RSVD_7 63
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#define GPIO_RSVD_8 64
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#define GPIO_RSVD_9 65
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#define GPIO_RSVD_10 66
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#define GPIO_RSVD_11 67
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#define SPI0_IO_2 59
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#define SPI0_IO_3 60
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#define SPI0_MOSI 61
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#define SPI0_MISO 62
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#define SPI0_CS2_B 63
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#define SPI0_CS0_B 64
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#define SPI0_CS1_B 65
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#define SPI0_CLK 66
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#define SPI0_CLK_LOOPBK 67
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#define NUM_GPIO_COM0_PADS (GPIO_RSVD_11 - GPP_A0 + 1)
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#define NUM_GPIO_COM0_PADS (SPI0_CLK_LOOPBK - GPP_A0 + 1)
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/* Group D */
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#define GPP_D0 68
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@ -132,7 +132,7 @@
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#define GPP_D21 89
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#define GPP_D22 90
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#define GPP_D23 91
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#define GPIO_RSVD_12 92
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#define GSPI2_CLK_LOOPBK 92
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/* Group F */
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#define GPP_F0 93
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#define GPP_F1 94
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@ -188,7 +188,7 @@
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#define CNV_GNEN 142
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#define CNV_WFEN 143
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#define CNV_WCEN 144
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#define CNV_BT_HOST_WAKEB 145
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#define CNV_BT_HOST_WAKE_B 145
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#define CNV_BT_IF_SELECT 146
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#define vCNV_BT_UART_TXD 147
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#define vCNV_BT_UART_RXD 148
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@ -222,7 +222,7 @@
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#define vSSP2_SFRM 176
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#define vSSP2_TXD 177
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#define vSSP2_RXD 178
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#define vCNV_GNSS_HOST_WAKEB 179
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#define vCNV_GNSS_HOST_WAKE_B 179
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#define vSD3_CD_B 180
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#define NUM_GPIO_COM1_PADS (vSD3_CD_B - GPP_D0 + 1)
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@ -278,26 +278,26 @@
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#define GPP_E22 227
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#define GPP_E23 228
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/* Group Jtag */
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#define GPIO_RSVD_13 229
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#define GPIO_RSVD_14 230
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#define GPIO_RSVD_15 231
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#define GPIO_RSVD_16 232
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#define GPIO_RSVD_17 233
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#define GPIO_RSVD_18 234
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#define GPIO_RSVD_19 235
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#define GPIO_RSVD_20 236
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#define GPIO_RSVD_21 237
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#define PCH_TDO 229
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#define PCH_JTAGX 230
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#define PROC_PRDY_B 231
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#define PROC_PREQ_B 232
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#define CPU_TRST_B 233
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#define PCH_TDI 234
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#define PCH_TMS 235
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#define PCH_TCK 236
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#define ITP_PMODE 237
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/* Group HVMOS */
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#define GPIO_RSVD_22 238
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#define GPIO_RSVD_23 239
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#define GPIO_RSVD_24 240
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#define GPIO_RSVD_25 241
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#define GPIO_RSVD_26 242
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#define GPIO_RSVD_27 243
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#define EDP_BKLTEN 238
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#define EDP_BKLTCTL 239
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#define EDP_VDDEN 240
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#define SYS_PWROK 241
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#define SYS_RESET_B 242
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#define CL_RST_B 243
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#define NUM_GPIO_COM4_PADS (GPIO_RSVD_27 - GPP_C0 + 1)
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#define NUM_GPIO_COM4_PADS (CL_RST_B - GPP_C0 + 1)
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/* Group GPD */
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/* Group GPD */
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#define GPD0 244
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#define GPD1 245
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#define GPD2 246
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@ -316,27 +316,27 @@
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/* Group AZA */
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#define HDA_BCLK 256
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#define HDA_RSTB 257
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#define HDA_RST_B 257
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#define HDA_SYNC 258
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#define HDA_SDO 259
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#define HDA_SDI_0 260
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#define HDA_SDI_1 261
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#define SSP1_SFRM 262
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#define SSP1_TXD 263
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#define HDA_SDI0 260
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#define HDA_SDI1 261
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#define I2S1_SFRM 262
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#define I2S1_TXD 263
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/* Group CPU */
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#define GPIO_RSVD_28 264
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#define GPIO_RSVD_29 265
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#define GPIO_RSVD_30 266
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#define GPIO_RSVD_31 267
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#define GPIO_RSVD_32 268
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#define GPIO_RSVD_33 269
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#define GPIO_RSVD_34 270
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#define GPIO_RSVD_35 271
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#define GPIO_RSVD_36 272
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#define GPIO_RSVD_37 273
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#define GPIO_RSVD_38 274
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||||
#define HDACPU_SDI 264
|
||||
#define HDACPU_SDO 265
|
||||
#define HDACPU_SCLK 266
|
||||
#define PM_SYNC 267
|
||||
#define PECI_IO 268
|
||||
#define CPUPWRGD 269
|
||||
#define THRMTRIP_B 270
|
||||
#define PLTRST_CPU_B 271
|
||||
#define PM_DOWN 272
|
||||
#define TRIGGER_IN 273
|
||||
#define TRIGGER_OUT 274
|
||||
|
||||
#define NUM_GPIO_COM3_PADS (GPIO_RSVD_38 - HDA_BCLK + 1)
|
||||
#define NUM_GPIO_COM3_PADS (TRIGGER_OUT - HDA_BCLK + 1)
|
||||
|
||||
#define TOTAL_PADS 275
|
||||
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@
|
|||
#define GPP_A21 21
|
||||
#define GPP_A22 22
|
||||
#define GPP_A23 23
|
||||
#define GPIO_RSVD_0 24
|
||||
#define ESPI_CLK_LOOPBK 24
|
||||
|
||||
/* Group B */
|
||||
#define GPP_B0 25
|
||||
|
|
@ -80,10 +80,10 @@
|
|||
#define GPP_B21 46
|
||||
#define GPP_B22 47
|
||||
#define GPP_B23 48
|
||||
#define GPIO_RSVD_1 49
|
||||
#define GPIO_RSVD_2 50
|
||||
#define GSPI0_CLK_LOOPBK 49
|
||||
#define GSPI1_CLK_LOOPBK 50
|
||||
|
||||
#define NUM_GPIO_COM0_PADS (GPIO_RSVD_2 - GPP_A0 + 1)
|
||||
#define NUM_GPIO_COM0_PADS (GSPI1_CLK_LOOPBK - GPP_A0 + 1)
|
||||
|
||||
/* Group C */
|
||||
#define GPP_C0 51
|
||||
|
|
@ -148,22 +148,22 @@
|
|||
#define GPP_G7 106
|
||||
|
||||
/* AZA */
|
||||
#define GPIO_RSVD_3 107
|
||||
#define GPIO_RSVD_4 108
|
||||
#define GPIO_RSVD_5 109
|
||||
#define GPIO_RSVD_6 110
|
||||
#define GPIO_RSVD_7 111
|
||||
#define GPIO_RSVD_8 112
|
||||
#define GPIO_RSVD_9 113
|
||||
#define GPIO_RSVD_10 114
|
||||
#define HDA_BCLK 107
|
||||
#define HDA_RST_B 108
|
||||
#define HDA_SYNC 109
|
||||
#define HDA_SDO 110
|
||||
#define HDA_SDI0 111
|
||||
#define HDA_SDI1 112
|
||||
#define I2S1_SFRM 113
|
||||
#define I2S1_TXD 114
|
||||
|
||||
/* VGPIO_0 */
|
||||
#define CNV_BTEN 115
|
||||
#define CNV_GNEN 116
|
||||
#define CNV_WFEN 117
|
||||
#define CNV_WCEN 118
|
||||
#define CNV_BT_HOST_WAKEB 119
|
||||
#define vCNV_GNSS_HOST_WAKEB 120
|
||||
#define CNV_BT_HOST_WAKE_B 119
|
||||
#define vCNV_GNSS_HOST_WAKE_B 120
|
||||
#define vSD3_CD_B 121
|
||||
#define CNV_BT_IF_SELECT 122
|
||||
#define vCNV_BT_UART_TXD 123
|
||||
|
|
@ -181,11 +181,11 @@
|
|||
#define vUART0_TXD 135
|
||||
#define vUART0_RXD 136
|
||||
#define vUART0_CTS_B 137
|
||||
#define vUART0_RTSB 138
|
||||
#define vUART0_RTS_B 138
|
||||
#define vISH_UART0_TXD 139
|
||||
#define vISH_UART0_RXD 140
|
||||
#define vISH_UART0_CTS_B 141
|
||||
#define vISH_UART0_RTSB 142
|
||||
#define vISH_UART0_RTS_B 142
|
||||
#define vISH_UART1_TXD 143
|
||||
#define vISH_UART1_RXD 144
|
||||
#define vISH_UART1_CTS_B 145
|
||||
|
|
@ -296,41 +296,41 @@
|
|||
#define GPP_F23 239
|
||||
|
||||
/* SPI */
|
||||
#define GPIO_RSVD_11 240
|
||||
#define GPIO_RSVD_12 241
|
||||
#define GPIO_RSVD_13 242
|
||||
#define GPIO_RSVD_14 243
|
||||
#define GPIO_RSVD_15 244
|
||||
#define GPIO_RSVD_16 245
|
||||
#define GPIO_RSVD_17 246
|
||||
#define GPIO_RSVD_18 247
|
||||
#define GPIO_RSVD_19 248
|
||||
#define SPI0_IO_2 240
|
||||
#define SPI0_IO_3 241
|
||||
#define SPI0_MOSI 242
|
||||
#define SPI0_MISO 243
|
||||
#define SPI0_CS2_B 244
|
||||
#define SPI0_CS0_B 245
|
||||
#define SPI0_CS1_B 246
|
||||
#define SPI0_CLK 247
|
||||
#define SPI0_CLK_LOOPBK 248
|
||||
|
||||
#define NUM_GPIO_COM3_PADS (GPIO_RSVD_19 - GPP_K0 + 1)
|
||||
#define NUM_GPIO_COM3_PADS (SPI0_CLK_LOOPBK - GPP_K0 + 1)
|
||||
|
||||
/* CPU */
|
||||
#define GPIO_RSVD_20 249
|
||||
#define GPIO_RSVD_21 250
|
||||
#define GPIO_RSVD_22 251
|
||||
#define GPIO_RSVD_23 252
|
||||
#define GPIO_RSVD_24 253
|
||||
#define GPIO_RSVD_25 254
|
||||
#define GPIO_RSVD_26 255
|
||||
#define GPIO_RSVD_27 256
|
||||
#define GPIO_RSVD_28 257
|
||||
#define GPIO_RSVD_29 258
|
||||
#define GPIO_RSVD_30 259
|
||||
#define HDACPU_SDI 249
|
||||
#define HDACPU_SDO 250
|
||||
#define HDACPU_SCLK 251
|
||||
#define PM_SYNC 252
|
||||
#define PECI_IO 253
|
||||
#define CPUPWRGD 254
|
||||
#define THRMTRIP_B 255
|
||||
#define PLTRST_CPU_B 256
|
||||
#define PM_DOWN 257
|
||||
#define TRIGGER_IN 258
|
||||
#define TRIGGER_OUT 259
|
||||
|
||||
/* JTAG */
|
||||
#define GPIO_RSVD_31 260
|
||||
#define GPIO_RSVD_32 261
|
||||
#define GPIO_RSVD_33 262
|
||||
#define GPIO_RSVD_34 263
|
||||
#define GPIO_RSVD_35 264
|
||||
#define GPIO_RSVD_36 265
|
||||
#define GPIO_RSVD_37 266
|
||||
#define GPIO_RSVD_38 267
|
||||
#define GPIO_RSVD_39 268
|
||||
#define PCH_TDO 260
|
||||
#define PCH_JTAGX 261
|
||||
#define PROC_PRDY_B 262
|
||||
#define PROC_PREQ_B 263
|
||||
#define CPU_TRST_B 264
|
||||
#define PCH_TDI 265
|
||||
#define PCH_TMS 266
|
||||
#define PCH_TCK 267
|
||||
#define ITP_PMODE 268
|
||||
|
||||
/* Group I */
|
||||
#define GPP_I0 269
|
||||
|
|
@ -348,9 +348,9 @@
|
|||
#define GPP_I12 281
|
||||
#define GPP_I13 282
|
||||
#define GPP_I14 283
|
||||
#define GPIO_RSVD_40 284
|
||||
#define GPIO_RSVD_41 285
|
||||
#define GPIO_RSVD_42 286
|
||||
#define SYS_PWROK 284
|
||||
#define SYS_RESET_B 285
|
||||
#define CL_RST_B 286
|
||||
|
||||
/* Group J */
|
||||
#define GPP_J0 287
|
||||
|
|
@ -368,7 +368,7 @@
|
|||
|
||||
#define NUM_GPIO_COM4_PADS (GPP_J11 - GPP_I0 + 1)
|
||||
|
||||
/* Group GPD */
|
||||
/* Group GPD */
|
||||
#define GPD0 299
|
||||
#define GPD1 300
|
||||
#define GPD2 301
|
||||
|
|
|
|||
Loading…
Reference in a new issue