kunimitsu: Clean up devicetree.cb
Fix the PCI device list comments to be consistent between mainboards and remove unused and incorrect register settings. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: Ib1c0eb80c57661502a4d4cfb4622a34effaa1c4a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 17c4f0d306194e7086f39f7ab560841999c318d8 Original-Change-Id: Ia1c138e52cbc3e81c0d12aa97d7f564e723d61f9 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297339 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11562 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
Patrick Georgi
parent
d96f830786
commit
1c2de9fc3d
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@ -1,19 +1,54 @@
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chip soc/intel/skylake
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# SerialIO device modes
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register "SerialIoDevMode" = "{ \
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[PchSerialIoIndexI2C0] = PchSerialIoPci, \
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[PchSerialIoIndexI2C1] = PchSerialIoPci, \
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[PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
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[PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
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[PchSerialIoIndexI2C4] = PchSerialIoPci, \
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[PchSerialIoIndexI2C5] = PchSerialIoPci, \
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[PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
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[PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
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[PchSerialIoIndexUart0] = PchSerialIoPci, \
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[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
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[PchSerialIoIndexUart2] = PchSerialIoPci, \
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}"
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# Enable deep Sx states
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register "deep_s3_enable" = "1"
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register "deep_s5_enable" = "1"
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register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "gpe0_dw0" = "GPP_C"
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register "gpe0_dw1" = "GPP_D"
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register "gpe0_dw2" = "GPP_E"
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# EC host command range is in 0x800-0x8ff
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register "gen1_dec" = "0x00fc0801"
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# FSP Configuration
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register "ProbelessTrace" = "0"
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register "EnableLan" = "0"
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register "EnableSata" = "0"
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register "SataSalpSupport" = "0"
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register "SataMode" = "0"
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register "SataPortsEnable[0]" = "0"
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register "EnableAzalia" = "1"
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register "DspEnable" = "1"
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register "IoBufferOwnership" = "3"
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register "EnableTraceHub" = "0"
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register "XdciEnable" = "0"
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register "SsicPortEnable" = "0"
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register "SmbusEnable" = "1"
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register "Cio2Enable" = "0"
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register "ScsEmmcEnabled" = "1"
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register "ScsEmmcHs400Enabled" = "1"
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register "ScsSdCardEnabled" = "2"
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register "IshEnable" = "0"
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register "PttSwitch" = "0"
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register "InternalGfx" = "1"
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register "SkipExtGfxScan" = "1"
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register "Device4Enable" = "1"
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# Enable Root port 1 and 5.
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register "PcieRpEnable[0]" = "1"
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register "PcieRpEnable[4]" = "1"
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# Enable CLKREQ#
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register "PcieRpClkReqSupport[0]" = "1"
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register "PcieRpClkReqSupport[4]" = "1"
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# RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2#
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register "PcieRpClkReqNumber[0]" = "1"
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register "PcieRpClkReqNumber[4]" = "2"
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register "PortUsb20Enable[0]" = "1" # Type-C Port 1
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register "PortUsb20Enable[1]" = "1" # Type-C Port 2
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@ -27,106 +62,43 @@ chip soc/intel/skylake
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register "PortUsb30Enable[2]" = "1" # Type-A Port (card)
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register "PortUsb30Enable[3]" = "1" # Type-A Port (board)
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register "pirqa_routing" = "0x8b"
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register "pirqb_routing" = "0x8a"
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register "pirqc_routing" = "0x8b"
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register "pirqd_routing" = "0x8b"
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register "pirqe_routing" = "0x80"
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register "pirqf_routing" = "0x80"
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register "pirqg_routing" = "0x80"
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register "pirqh_routing" = "0x80"
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# Must leave UART0 enabled or SD/eMMC will not work as PCI
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register "SerialIoDevMode" = "{ \
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[PchSerialIoIndexI2C0] = PchSerialIoPci, \
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[PchSerialIoIndexI2C1] = PchSerialIoPci, \
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[PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
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[PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
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[PchSerialIoIndexI2C4] = PchSerialIoPci, \
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[PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
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[PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
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[PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
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[PchSerialIoIndexUart0] = PchSerialIoPci, \
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[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
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[PchSerialIoIndexUart2] = PchSerialIoPci, \
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}"
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# EC range is 0x800-0x9ff
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x00fc0901"
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# Pcie RootPort
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register "PcieRpEnable[0]" = "1"
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register "PcieRpEnable[4]" = "1"
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register "PcieRpClkReqNumber[0]" = "1"
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register "PcieRpClkReqNumber[4]" = "2"
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register "PcieRpClkReqSupport[0]" = "1"
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register "PcieRpClkReqSupport[4]" = "1"
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# GPE configuration
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register "gpe0_en_1" = "0x00000000"
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# EC_SCI is GPIO36
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register "gpe0_en_2" = "0x00000010"
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register "gpe0_en_3" = "0x00000000"
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register "gpe0_en_4" = "0x00000000"
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# Memory related
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register "ProbelessTrace" = "0"
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# Lan
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register "EnableLan" = "0"
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# SATA related
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register "EnableSata" = "0"
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register "SataSalpSupport" = "0"
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register "SataMode" = "0"
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register "SataPortsEnable[0]" = "0"
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register "SsicPortEnable" = "0"
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# Audio related
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register "EnableAzalia" = "1"
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register "EnableTraceHub" = "0"
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register "DspEnable" = "1"
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# I/O Buffer Ownership:
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# 0: HD-A Link
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# 1 Shared, HD-A Link and I2S Port
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# 3: I2S Ports
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register "IoBufferOwnership" = "3"
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# SMBUS
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register "SmbusEnable" = "1"
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# Camera
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register "Cio2Enable" = "0"
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# eMMC
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register "ScsEmmcEnabled" = "1"
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register "ScsEmmcHs400Enabled" = "1"
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register "ScsSdCardEnabled" = "2"
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# Integrated Sensor
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register "IshEnable" = "0"
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# Enable deep Sx states
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register "deep_s3_enable" = "0"
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register "deep_s5_enable" = "1"
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# CPU Thermal participant device
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register "Device4Enable" = "1"
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# XDCI controller
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register "XdciEnable" = "0"
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device cpu_cluster 0 on
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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# Refered from SKL EDS Vol 1 : Page No: 31-32
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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device pci 14.0 on end # USB 3.0 xHCI Controller
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device pci 14.1 off end # USB Device Controller (OTG)
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device pci 14.0 on end # USB xHCI
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.2 on end # Thermal Subsystem
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device pci 15.0 on end # I2C Controller #0
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device pci 15.1 on end # I2C Controller #1
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device pci 15.2 on end # I2C Controller #2
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device pci 15.3 on end # I2C Controller #3
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device pci 15.0 on end # I2C #0
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device pci 15.1 on end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE Redirection (IDE-R)
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device pci 16.3 off end # Management Engine Keyboard and Text (KT) Redirection
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device pci 16.4 off end # Management Engine Intel MEI #3
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device pci 17.0 off end # SATA Controller
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device pci 19.0 on end # UART Controller #2
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device pci 19.1 on end # I2C Controller #5
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device pci 19.2 on end # I2C Controller #4
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 17.0 off end # SATA
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device pci 19.0 on end # UART #2
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device pci 19.1 off end # I2C #5
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device pci 19.2 on end # I2C #4
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device pci 1c.0 on end # PCI Express Port 1
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device pci 1c.1 off end # PCI Express Port 2
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device pci 1c.2 off end # PCI Express Port 3
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@ -140,20 +112,24 @@ chip soc/intel/skylake
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device pci 1d.2 off end # PCI Express Port 11
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device pci 1d.3 off end # PCI Express Port 12
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device pci 1e.0 on end # UART #0
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device pci 1e.1 on end # UART #1
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device pci 1e.2 on end # SPI #0
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device pci 1e.1 off end # UART #1
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device pci 1e.2 off end # GSPI #0
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device pci 1e.3 off end # GSPI #1
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device pci 1e.4 on end # eMMC
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device pci 1e.5 off end # SDIO
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device pci 1e.6 on end # SDCard
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device pci 1f.0 on
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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end
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end # LPC Interface
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device pci 1f.2 on end # Power Management Controller
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device pci 1f.3 on end # Intel High Definition Audio (Intel HD Audio) (Audio, Voice, Speech)
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device pci 1f.4 on end # SMBus Controller
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device pci 1f.5 on end # SPI
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device pci 1f.6 off end # GbE Controller
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device pci 1f.3 on end # Intel HDA
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # PCH SPI
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device pci 1f.6 off end # GbE
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end
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end
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