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cosmetic comment changes. 

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2010-05-19 18:39:23 +00:00 committed by Stefan Reinauer
parent ace2dc3ac1
commit 1c3c0faabc
1 changed files with 8 additions and 9 deletions
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15
src/include/cpu/x86/cache.h
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@ -20,18 +20,17 @@
#ifndef CPU_X86_CACHE #ifndef CPU_X86_CACHE
#define CPU_X86_CACHE #define CPU_X86_CACHE
/* the memory clobber prevents the GCC from reordering the read/write order /*
of CR0 */ * Need two versions because ROMCC chokes on certain clobbers:
* cache.h:29.71: cache.h:60.24: earlymtrr.c:117.23: romstage.c:144.33:
* 0x1559920 asm Internal compiler error: lhs 1 regcm == 0
*/
#if defined(__GNUC__) #if defined(__GNUC__)
/* /* The memory clobber prevents the GCC from reordering the read/write order
Need this because ROMCC fails here with: * of CR0
cache.h:29.71: cache.h:60.24: earlymtrr.c:117.23: romstage.c:144.33:
0x1559920 asm Internal compiler error: lhs 1 regcm == 0
*/ */
static inline unsigned long read_cr0(void) static inline unsigned long read_cr0(void)
{ {
unsigned long cr0; unsigned long cr0;