Remove the Embedded Planet board.
Signed-off-by: Ronald G. Minnich <rminich@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4710 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
Myles Watson
parent
6cc9c0ad28
commit
1c53d771c1
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@ -38,8 +38,6 @@ config VENDOR_DIGITAL_LOGIC
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bool "DIGITAL-LOGIC"
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config VENDOR_EAGLELION
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bool "EagleLion"
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config VENDOR_EMBEDDED_PLANET
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bool "Embedded Planet"
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config VENDOR_EMULATION
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bool "Emulation"
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config VENDOR_GIGABYTE
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@ -182,11 +180,6 @@ config MAINBOARD_VENDOR
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default "EagleLion"
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depends on VENDOR_EAGLELION
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config MAINBOARD_VENDOR
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string
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default "Embedded Planet"
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depends on VENDOR_EMBEDDED_PLANET
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config MAINBOARD_VENDOR
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string
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default "Emulation"
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@ -349,7 +342,6 @@ source "src/mainboard/compaq/Kconfig"
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source "src/mainboard/dell/Kconfig"
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source "src/mainboard/digitallogic/Kconfig"
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source "src/mainboard/eaglelion/Kconfig"
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source "src/mainboard/embeddedplanet/Kconfig"
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source "src/mainboard/emulation/Kconfig"
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source "src/mainboard/gigabyte/Kconfig"
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source "src/mainboard/hp/Kconfig"
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@ -361,7 +353,6 @@ source "src/mainboard/jetway/Kconfig"
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source "src/mainboard/kontron/Kconfig"
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source "src/mainboard/lippert/Kconfig"
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source "src/mainboard/mitac/Kconfig"
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source "src/mainboard/motorola/Kconfig"
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source "src/mainboard/msi/Kconfig"
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source "src/mainboard/nec/Kconfig"
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source "src/mainboard/newisys/Kconfig"
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@ -1 +0,0 @@
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#
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@ -1,27 +0,0 @@
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##
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## Config file for the Embedded Planet EP405PC Computing Engine
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##
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##
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## Early board initialization, called from ppc_main()
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##
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initobject init.c
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arch ppc end
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chip cpu/ppc/ppc4xx
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device pci_domain 0 on
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device pci 0.0 on end
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chip southbridge/winbond/w83c553
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device pci 9.0 on end # ISA bridge
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device pci 9.1 on end # IDE contoller
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end
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device pci e.0 on end
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end
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end
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##
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## Build the objects we have code for in this directory.
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##
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addaction coreboot.a "$(CONFIG_CROSS_COMPILE)ranlib coreboot.a"
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makedefine CFLAGS += -msoft-float
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@ -1,153 +0,0 @@
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##
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## Config file for the Embedded Planet EP405PC Computing Engine
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##
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uses CONFIG_PCIC0_CFGADDR
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uses CONFIG_CBFS
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uses CONFIG_ARCH_X86
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uses CONFIG_PCIC0_CFGDATA
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uses CONFIG_ISA_IO_BASE
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uses CONFIG_ISA_MEM_BASE
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uses CONFIG_TTYS0_BASE
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uses CONFIG_IO_BASE
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uses CONFIG_CPU_OPT
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uses CONFIG_CROSS_COMPILE
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uses CONFIG_HAVE_OPTION_TABLE
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uses CONFIG_COMPRESS
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uses CONFIG_CHIP_CONFIGURE
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uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
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uses CONFIG_USE_INIT
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uses CONFIG_CONSOLE_SERIAL8250
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uses CONFIG_TTYS0_BAUD CONFIG_TTYS0_DIV
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uses CONFIG_NO_POST
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uses CONFIG_IDE
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uses CONFIG_FS_PAYLOAD
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uses CONFIG_FS_EXT2
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uses CONFIG_FS_ISO9660
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uses CONFIG_FS_FAT
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uses CONFIG_COMPRESSED_PAYLOAD_LZMA
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uses CONFIG_PRECOMPRESSED_PAYLOAD
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uses CONFIG_AUTOBOOT_CMDLINE
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uses CONFIG_SYS_CLK_FREQ
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uses CONFIG_IDE_BOOT_DRIVE
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#uses CONFIG_IDE_SWAB
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uses CONFIG_IDE_OFFSET
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uses CONFIG_ROM_SIZE
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uses CONFIG_ROM_IMAGE_SIZE
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uses CONFIG_RESET
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uses CONFIG_EXCEPTION_VECTORS
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uses CONFIG_ROMBASE
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uses CONFIG_ROMSTART
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uses CONFIG_RAMBASE
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#uses CONFIG_RAMSTART
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uses CONFIG_EMBEDDED_RAM_SIZE
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uses CONFIG_STACK_SIZE CONFIG_HEAP_SIZE
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uses CONFIG_MAINBOARD
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uses CONFIG_MAINBOARD_VENDOR
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uses CONFIG_MAINBOARD_PART_NUMBER
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uses COREBOOT_EXTRA_VERSION
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uses CONFIG_CROSS_COMPILE
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uses CC
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uses HOSTCC
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uses CONFIG_OBJCOPY
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##
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## Set PCI configuration register addresses
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##
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default CONFIG_PCIC0_CFGADDR=0xeec00000
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default CONFIG_PCIC0_CFGDATA=0xeec00004
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##
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## Set PCI/ISA I/O and memory base address
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##
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default CONFIG_ISA_IO_BASE=0xe8000000
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default CONFIG_ISA_MEM_BASE=0x80000000
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default CONFIG_IO_BASE=CONFIG_ISA_IO_BASE
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##
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## HACK ALERT: the UART0 registers are not in the PCI I/O address space
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## but both IDE and UART use the same routines for I/O (inb/outb). To get
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## around this we set TTYSO_BASE to the difference between the two.
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##
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default CONFIG_TTYS0_BASE=0xef600300-CONFIG_ISA_IO_BASE
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## Enable PPC405 instructions
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default CONFIG_CPU_OPT="-mcpu=405"
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#default CONFIG_CPU_OPT=""
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default CONFIG_ARCH_X86=0
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## Use stage 1 initialization code
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default CONFIG_USE_INIT=1
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## Use chip configuration
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default CONFIG_CHIP_CONFIGURE=1
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## We don't use compressed image
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default CONFIG_COMPRESS=0
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## Turn off POST codes
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default CONFIG_NO_POST=1
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## Enable serial console
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default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
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default CONFIG_CONSOLE_SERIAL8250=1
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# Divisor of 69 == 9600 baud due to weird clocking
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default CONFIG_TTYS0_DIV=69
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default CONFIG_TTYS0_BAUD=9600
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## Boot linux from IDE
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default CONFIG_IDE=1
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default CONFIG_FS_PAYLOAD=1
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default CONFIG_FS_EXT2=1
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default CONFIG_FS_ISO9660=1
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default CONFIG_FS_FAT=1
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default CONFIG_AUTOBOOT_CMDLINE="hda1:/vmlinuz"
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default CONFIG_ROM_SIZE=1048576
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default CONFIG_ROM_IMAGE_SIZE=160*1024
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## Board has fixed size RAM
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default CONFIG_EMBEDDED_RAM_SIZE=64*1024*1024
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## Coreboot C code runs at this location in RAM
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default CONFIG_RAMBASE=0x00100000
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##
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## Use a 64K stack
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##
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default CONFIG_STACK_SIZE=0x10000
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##
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## Use a 64K heap
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##
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default CONFIG_HEAP_SIZE=0x10000
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##
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## System clock
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##
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default CONFIG_SYS_CLK_FREQ=33
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##
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default CONFIG_ROMBASE=0xfff00000
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## Reset vector address
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default CONFIG_RESET=0xfffffffc
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## Exception vectors
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default CONFIG_EXCEPTION_VECTORS=CONFIG_ROMBASE+0x100
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## coreboot ROM start address
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default CONFIG_ROMSTART=0xfff03000
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## coreboot C code runs at this location in RAM
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default CONFIG_RAMBASE=0x00100000
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### End Options.lb
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#
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# CBFS
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#
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#
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default CONFIG_CBFS=1
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end
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@ -1,17 +0,0 @@
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chip cpu/ppc/ppc4xx
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device pci_domain 0 on
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device pci 0.0 on end
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chip southbridge/winbond/w83c553
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device pci 9.0 on end # ISA bridge
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device pci 9.1 on end # IDE contoller
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end
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device pci e.0 on end
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end
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end
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##
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## Build the objects we have code for in this directory.
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##
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addaction coreboot.a "$(CONFIG_CROSS_COMPILE)ranlib coreboot.a"
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makedefine CFLAGS += -msoft-float
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@ -1,89 +0,0 @@
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; bdiGDB configuration file for the Embedded Planet EP405PC
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; ---------------------------------------------------------
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;
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[INIT]
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; init core register
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WSPR 954 0x00000000 ;DCWR: Disable data cache write-thru
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WSPR 1018 0x00000000 ;DCCR: Disable data cache
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WSPR 1019 0x00000000 ;ICCR: Disable instruction cache
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WSPR 981 0x00000000 ;EVPR: Exception Vector Table @0x00000000
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; Setup SDRAM Controller
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WDCR 16 0x00000080 ;Select SDRAM0_TR
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WDCR 17 0x010E8016 ;TR: SDRAM Timing Register
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WDCR 16 0x00000040 ;Select SDRAM0_B0CR
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WDCR 17 0x00084001 ;Select bank 0
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WDCR 16 0x00000030 ;Select SDRAM0_RTR
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WDCR 17 0x08080000 ;RTR: Refresh Timing Register
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WDCR 16 0x00000094 ;Select SDRAM0_ECCCFG
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WDCR 17 0x00000000 ;ECC: Disabled
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WDCR 16 0x00000034 ;Select SDRAM0_PMIT
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WDCR 17 0x0F000000 ;PMIT: Power Management Idle Timer
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DELAY 1 ;Wait for SDRAM powerup
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WDCR 16 0x00000020 ;Select SDRAM0_CFG
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WDCR 17 0x80C00000 ;CFG: Enable
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; MMU
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WM32 0xf0 0x00000000 ;invalidate page table base
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; EBC
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WDCR 0x12 0x00000004 ;Select EBC0_B4CR
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WDCR 0x13 0xF4058000 ;Set NVRTC/BCSR
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WDCR 0x12 0x00000014 ;Select EBC0_B4AP
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WDCR 0x13 0x04050000 ;Set NVRTC/BCSR timing
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WM8 0xF4000003 0x20 ;Enable UART0
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WM8 0xF4000009 0x07 ;LED
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DELAY 500
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WM8 0xF4000009 0x0b ;LED
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DELAY 500
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WM8 0xF4000009 0x0d ;LED
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DELAY 500
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WM8 0xF4000009 0x0e ;LED
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DELAY 500
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[TARGET]
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JTAGCLOCK 0 ;use 16 MHz JTAG clock
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CPUTYPE 405 ;the used target CPU type
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BDIMODE AGENT ;the BDI working mode (LOADONLY | AGENT)
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;WAKEUP 3000 ;wakeup time after reset
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BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint
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STEPMODE JTAG ;JTAG or HWBP, HWPB uses one or two hardware breakpoints
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VECTOR CATCH ;catch unhandled exceptions
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MMU XLAT 0xC0000000 ;enable virtual address mode
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PTBASE 0x000000f0 ;address where kernel/user stores pointer to page table
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SIO 2002 9600 ;TCP port for serial IO
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;SIO 2002 115200 ;TCP port for serial IO
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;REGLIST SPR ;select register to transfer to GDB
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;REGLIST ALL ;select register to transfer to GDB
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;SCANPRED 2 2 ;JTAG devices connected before PPC400
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;SCANSUCC 3 3 ;JTAG devices connected after PPC400
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[HOST]
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IP 10.0.1.2
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FORMAT ELF
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FILE coreboot.elf
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;START 0x200000
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LOAD MANUAL ;load code MANUAL or AUTO after reset
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DEBUGPORT 2001
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DUMP dump.bin ;Linux: dump.bin must already exist and public writable
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[FLASH]
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WORKSPACE 0x00004000 ;workspace in target RAM for fast programming algorithm
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CHIPTYPE AM29BX16 ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16)
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CHIPSIZE 0x400000 ;The size of one flash chip in bytes (e.g. AM29F040 = 0x80000)
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BUSWIDTH 16 ;The width of the flash memory bus in bits (8 | 16 | 32)
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ERASE 0xFFF80000 ;erase sector 0 of flash in U7 (AM29F040)
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ERASE 0xFFF90000 ;erase sector 1 of flash
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ERASE 0xFFFA0000 ;erase sector 2 of flash
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ERASE 0xFFFB0000 ;erase sector 3 of flash
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ERASE 0xFFFC0000 ;erase sector 4 of flash
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ERASE 0xFFFD0000 ;erase sector 5 of flash
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ERASE 0xFFFE0000 ;erase sector 6 of flash
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ERASE 0xFFFF0000 ;erase sector 7 of flash
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[REGS]
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IDCR1 0x010 0x011 ;MEMCFGADR and MEMCFGDATA
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IDCR2 0x012 0x013 ;EBCCFGADR and EBCCFGDATA
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IDCR3 0x014 0x015 ;KIAR and KIDR
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FILE reg405gp.def
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@ -1,114 +0,0 @@
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/*
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* Copyright (C) 2003, Greg Watson <gwatson@lanl.gov>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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/*
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* Do very early board initialization:
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*
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* - Configure External Bus (EBC)
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* - Setup Flash
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* - Setup NVRTC
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* - Setup Board Control and Status Registers (BCSR)
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* - Enable UART0 for debugging
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*/
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#include <ppc_asm.tmpl>
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#include <ppc.h>
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#include <ppc4xx.h>
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#include <arch/io.h>
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#include <timer.h>
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void
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board_init(void)
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{
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/*
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* Configure Inerrupt Controller
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*/
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr(uicer, 0x00000000); /* disable all ints */
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mtdcr(uiccr, 0x00000000); /* set all to be non-critical */
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mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
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mtdcr(uictr, 0x10000000); /* set int trigger levels */
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mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest pri */
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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/*
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* Configure FLASH
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*/
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mtebc(pb0cr, 0xFC0DC000);
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mtebc(pb0ap, 0x02000000);
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/*
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* Configure NVTRC/BCSR
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*/
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mtebc(pb4cr, 0xF4058000);
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mtebc(pb4ap, 0x04050000);
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/*
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* Board Control and Status Register (BCSR) setup
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*/
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/*
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* BCSR1 - PCI Control
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*/
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out_8((unsigned char *)0xF4000001, 0x80);
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/*
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* BCSR2 - FLASH, NVRAM and POR Control
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*/
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out_8((unsigned char *)0xF4000002, 0x9C);
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/*
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* BCSR3 - FENET and UART
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*/
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out_8((unsigned char *)0xF4000003, 0xf0);
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/*
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* BCSR4 - PCI Status and Masking
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*/
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out_8((unsigned char *)0xF4000004, 0x00);
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/*
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* BCSR5 - XIRQ Select
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*/
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out_8((unsigned char *)0xF4000005, 0x00);
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/*
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* BCSR6 - XIRQ Routing
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*/
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out_8((unsigned char *)0xF4000006, 0x07);
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/*
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* Cycle LEDs to show something is happening...
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*/
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out_8((unsigned char *)0xF4000009, 0x07);
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udelay(100000);
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out_8((unsigned char *)0xF4000009, 0x0B);
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udelay(100000);
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out_8((unsigned char *)0xF4000009, 0x0D);
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udelay(100000);
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out_8((unsigned char *)0xF4000009, 0x0E);
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}
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void
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board_init2(void)
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{
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}
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@ -1,81 +0,0 @@
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# Config file for Embedded Planet EP405PC board
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# This will make a target directory of ./ep405pc
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target ep405pc
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mainboard embeddedplanet/ep405pc
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romimage "fallback"
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## Enable PPC405 instructions
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option CONFIG_CPU_OPT="-mcpu=405"
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## use a cross compiler
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#option CONFIG_CROSS_COMPILE="powerpc-ibm-eabi-"
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## Use stage 1 initialization code
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option CONFIG_USE_INIT=1
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## Use chip configuration
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option CONFIG_CHIP_CONFIGURE=1
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## We don't use compressed image
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option CONFIG_COMPRESS=0
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## Turn off POST codes
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option CONFIG_NO_POST=1
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## Enable serial console
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option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
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option CONFIG_CONSOLE_SERIAL8250=1
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||||
# Divisor of 69 == 9600 baud due to weird clocking
|
||||
option CONFIG_TTYS0_DIV=69
|
||||
option CONFIG_TTYS0_BAUD=9600
|
||||
|
||||
## Boot linux from IDE
|
||||
option CONFIG_IDE=1
|
||||
option CONFIG_FS_PAYLOAD=1
|
||||
option CONFIG_FS_EXT2=1
|
||||
option CONFIG_FS_ISO9660=1
|
||||
option CONFIG_FS_FAT=1
|
||||
option CONFIG_AUTOBOOT_CMDLINE="hda1:/vmlinuz"
|
||||
|
||||
option CONFIG_ROM_SIZE=1024*1024
|
||||
|
||||
## Board has fixed size RAM
|
||||
option CONFIG_EMBEDDED_RAM_SIZE=64*1024*1024
|
||||
|
||||
## Coreboot C code runs at this location in RAM
|
||||
option CONFIG_RAMBASE=0x00100000
|
||||
|
||||
##
|
||||
## Use a 64K stack
|
||||
##
|
||||
option CONFIG_STACK_SIZE=0x10000
|
||||
|
||||
##
|
||||
## Use a 64K heap
|
||||
##
|
||||
option CONFIG_HEAP_SIZE=0x10000
|
||||
|
||||
##
|
||||
## System clock
|
||||
##
|
||||
option CONFIG_SYS_CLK_FREQ=33
|
||||
|
||||
##
|
||||
option CONFIG_ROMBASE=0xfff00000
|
||||
|
||||
## Reset vector address
|
||||
option CONFIG_RESET=0xfffffffc
|
||||
|
||||
## Exception vectors
|
||||
option CONFIG_EXCEPTION_VECTORS=CONFIG_ROMBASE+0x100
|
||||
|
||||
## coreboot ROM start address
|
||||
option CONFIG_ROMSTART=0xfff03000
|
||||
|
||||
## coreboot C code runs at this location in RAM
|
||||
option CONFIG_RAMBASE=0x00100000
|
||||
|
||||
end
|
||||
|
||||
buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
|
||||
Loading…
Reference in New Issue