Clean up Geode GX2 comments, whitespace and coding style. Trivial.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6208 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Nils Jacobs
Peter Stuge
parent
88929f9bf4
commit
1c6d4e6055
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@ -11,46 +11,35 @@
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#include <cpu/x86/msr.h>
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#include <cpu/x86/cache.h>
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#if 0
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void
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bug645(void){
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void bug645(void)
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{
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msr_t msr;
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rdmsr(CPU_ID_CONFIG);
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msr.whatever |= ID_CONFIG_SERIAL_SET;
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wrmsr(msr);
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}
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void
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bug573(void){
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void bug573(void)
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{
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msr_t msr;
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msr = rdmsr(MC_GLD_MSR_PM);
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msr.eax &= 0xfff3;
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wrmsr(MC_GLD_MSR_PM);
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}
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#endif
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/**************************************************************************
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*
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* pcideadlock
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/* pcideadlock
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*
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* Bugtool #465 and #609
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* PCI cache deadlock
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* There is also fix code in cache and PCI functions. This bug is very is pervasive.
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*
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* Entry:
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* Exit:
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* Modified:
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*
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**************************************************************************/
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static void
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pcideadlock(void)
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*/
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static void pcideadlock(void)
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{
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msr_t msr;
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/*
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* forces serialization of all load misses. Setting this bit prevents the
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/* forces serialization of all load misses. Setting this bit prevents the
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* DM pipe from backing up if a read request has to be held up waiting
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* for PCI writes to complete.
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*/
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@ -78,20 +67,12 @@ pcideadlock(void)
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wrmsr( CPU_RCONF_E0_FF, msr);
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}
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/****************************************************************************
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*
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* CPUbug784
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/* CPUbug784
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*
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* Bugtool #784 + #792
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*
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* Fix CPUID instructions for < 3.0 CPUs
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*
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* Entry:
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* Exit:
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* Modified:
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*
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****************************************************************************/
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*/
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static void bug784(void)
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{
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msr_t msr;
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@ -120,19 +101,14 @@ static void bug784(void)
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}
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/* cpubug 1398: enable MC if we KNOW we have DDR*/
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/**************************************************************************
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*
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* CPUbugIAENG1398
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/* CPUbugIAENG1398
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*
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* ClearQuest #IAENG1398
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* The MC can not be enabled with SDR memory but can for DDR. Enable for
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* DDR here if the setup token is "Default"
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* Add this back to core by default once 2.0 CPUs are not supported.
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* Entry:
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* Exit:
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* Modified:
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*
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**************************************************************************/
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*/
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static void eng1398(void)
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{
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msr_t msr;
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@ -150,22 +126,14 @@ static void eng1398(void)
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wrmsr(MC_GLD_MSR_PM, msr);
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}
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/***************************************************************************
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*
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* CPUbugIAENG2900
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/* CPUbugIAENG2900
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*
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* Clear Quest IAENG00002900, VSS 118.150
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*
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* BTB issue causes blue screen in windows, but the fix is required
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* for all operating systems.
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*
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* Entry:
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* Exit:
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* Modified:
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*
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**************************************************************************/
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static void
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eng2900(void)
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*/
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static void eng2900(void)
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{
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msr_t msr;
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@ -310,10 +278,11 @@ static void bug118339(void)
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msr.lo = 0x80004000;
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wrmsr(msrnum, msr);
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/* Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled */
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/* As per Todd Roberts in PBz1094 and PBz1095 */
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/* Moved from CPUREG to CPUBUG per Tom Sylla */
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msrnum = 0x04C000042; /* GLCP SETMCTL Register */;
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/* Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled
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* As per Todd Roberts in PBz1094 and PBz1095
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* Moved from CPUREG to CPUBUG per Tom Sylla
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*/
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msrnum = 0x04C000042; /* GLCP SETMCTL Register */
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msr = rdmsr(msrnum);
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msr.hi |= 8; /* Bit 35 = MCP_IN */
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wrmsr(msrnum, msr);
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@ -321,33 +290,24 @@ static void bug118339(void)
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/****************************************************************************/
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/***/
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/** DisableMemoryReorder*/
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/***/
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/** PBZ 3659:*/
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/** The MC reordered transactions incorrectly and breaks coherency.*/
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/** Disable reording and take a potential performance hit.*/
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/** This is safe to do here and not in MC init since there is nothing*/
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/** to maintain coherency with and the cache is not enabled yet.*/
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/***/
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/***/
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/** Entry:*/
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/** Exit:*/
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/** Modified:*/
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/***/
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/****************************************************************************/
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/* DisableMemoryReorder
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*
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* PBZ 3659:
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* The MC reordered transactions incorrectly and breaks coherency.
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* Disable reording and take a potential performance hit.
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* This is safe to do here and not in MC init since there is nothing
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* to maintain coherency with and the cache is not enabled yet.
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*/
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static void disablememoryreadorder(void)
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{
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msr_t msr;
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msr = rdmsr(MC_CF8F_DATA);
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msr = rdmsr(MC_CF8F_DATA);
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msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
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wrmsr(MC_CF8F_DATA, msr);
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}
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void
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cpubug(void)
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void cpubug(void)
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{
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msr_t msr;
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int rev;
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@ -5,7 +5,7 @@ void cpuRegInit (void)
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int msrnum;
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msr_t msr;
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/* Turn on BTM for early debug based on setup. */
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/* if (getnvram( TOKEN_BTM_DIAG_MODE) & 3) { */
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// if (getnvram( TOKEN_BTM_DIAG_MODE) & 3) {
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/* The following is only for diagnostics mode; do not use for OLPC */
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if (0) {
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/* Set Diagnostic Mode */
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@ -21,8 +21,8 @@ void cpuRegInit (void)
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wrmsr(msrnum, msr); /* exchange it to anything else to prevent this */
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/* Turn off debug clock */
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msrnum = 0x04C000016; /* DBG_CLK_CTL*/
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msr.lo = 0x00; /* No clock*/
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msrnum = 0x04C000016; /* DBG_CLK_CTL */
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msr.lo = 0x00; /* No clock */
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msr.hi = 0x00;
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wrmsr(msrnum, msr);
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@ -125,7 +125,7 @@ void cpuRegInit (void)
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}
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/* FPU impercise exceptions bit */
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/* if (getnvram( TOKEN_FPU_IE_ENABLE) != TVALUE_DISABLE) { */
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//if (getnvram( TOKEN_FPU_IE_ENABLE) != TVALUE_DISABLE) {
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{
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msrnum = CPU_FPU_MSR_MODE;
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msr = rdmsr(msrnum);
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@ -139,7 +139,7 @@ void cpuRegInit (void)
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* unless you're testing something.
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*/
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/* Allow NVRam to override DM Setup */
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/* if (getnvram( TOKEN_CACHE_DM_MODE) != 1) { */
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//if (getnvram( TOKEN_CACHE_DM_MODE) != 1) {
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{
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msrnum = CPU_DM_CONFIG0;
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msr = rdmsr(msrnum);
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@ -150,7 +150,7 @@ void cpuRegInit (void)
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* this unless you're testing something.
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*/
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/* Allow NVRam to override IM Setup */
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/* if (getnvram( TOKEN_CACHE_IM_MODE) ==1) { */
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//if (getnvram( TOKEN_CACHE_IM_MODE) ==1) {
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{
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msrnum = CPU_IM_CONFIG;
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msr = rdmsr(msrnum);
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@ -1,12 +1,9 @@
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/* ***************************************************************************/
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/* **/
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/* * StartTimer1*/
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/* **/
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/* * Entry: none*/
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/* * Exit: Starts Timer 1 for port 61 use*/
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/* * Destroys: Al,*/
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/* **/
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/* ***************************************************************************/
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/* StartTimer1
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*
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* Entry: none
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* Exit: Starts Timer 1 for port 61 use
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* Destroys: Al,
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*/
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static void StartTimer1(void)
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{
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outb(0x56, 0x43);
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@ -28,7 +28,6 @@
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/* GLCP_SYS_RSTPLL, Lower 32 bits */
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#define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26
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#define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26)
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#define GLCP_SYS_RSTPLL_LOCKWAIT 24
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#define GLCP_SYS_RSTPLL_HOLDCOUNT 16
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#define GLCP_SYS_RSTPLL_BYPASS 15
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@ -106,7 +105,6 @@
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#define MC_GLD_MSR_PM (MSR_MC + 0x2004)
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#define MC_CF07_DATA (MSR_MC + 0x18)
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#define CF07_UPPER_D1_SZ_SHIFT 28
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#define CF07_UPPER_D1_MB_SHIFT 24
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#define CF07_UPPER_D1_CB_SHIFT 20
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@ -115,7 +113,6 @@
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#define CF07_UPPER_D0_MB_SHIFT 8
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#define CF07_UPPER_D0_CB_SHIFT 4
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#define CF07_UPPER_D0_PSZ_SHIFT 0
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#define CF07_LOWER_REF_INT_SHIFT 8
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#define CF07_LOWER_LOAD_MODE_DDR_SET (1 << 28)
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#define CF07_LOWER_LOAD_MODE_DLL_RESET (1 << 27)
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@ -125,7 +122,6 @@
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#define CF07_LOWER_PROG_DRAM_SET (1 << 0)
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#define MC_CF8F_DATA (MSR_MC + 0x19)
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#define CF8F_UPPER_XOR_BS_SHIFT 19
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#define CF8F_UPPER_XOR_MB0_SHIFT 18
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#define CF8F_UPPER_XOR_BA1_SHIFT 17
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#define CF8F_UPPER_HOI_LOI_SET (1 << 1)
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#define MC_CF1017_DATA (MSR_MC + 0x1A)
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#define CF1017_LOWER_PM1_UP_DLY_SET (1 << 8)
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#define CF1017_LOWER_WR2DAT_SHIFT 0
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#define MC_CFCLK_DBUG (MSR_MC + 0x1D)
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#define CFCLK_UPPER_MTST_B2B_DIS_SET (1 << 2)
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#define CFCLK_UPPER_MTST_DQS_EN_SET (1 << 1)
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#define CFCLK_UPPER_MTEST_EN_SET (1 << 0)
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#define CFCLK_LOWER_MASK_CKE_SET1 (1 << 9)
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#define CFCLK_LOWER_MASK_CKE_SET0 (1 << 8)
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#define CFCLK_LOWER_SDCLK_SET (0x0F << 0)
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@ -161,30 +154,25 @@
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/* GLIU1 GLIU0 port2 */
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#define GLIU1_GLD_MSR_CAP (MSR_GLIU1 + 0x2000)
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#define GLIU1_GLD_MSR_PM (MSR_GLIU1 + 0x2004)
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#define GLIU1_GLD_MSR_COH (MSR_GLIU1 + 0x80)
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/* CPU ; does not need routing instructions since we are executing there. */
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#define CPU_GLD_MSR_CAP 0x2000
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#define CPU_GLD_MSR_CONFIG 0x2001
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#define CPU_GLD_MSR_PM 0x2004
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#define CPU_GLD_MSR_DIAG 0x2005
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#define DIAG_SEL1_MODE_SHIFT 16
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#define DIAG_SEL1_SET (1 << 31)
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#define DIAG_SEL0__MODE_SHIFT 0
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#define DIAG_SET0_SET (1 << 15)
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#define CPU_PF_BTB_CONF 0x1100
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#define BTB_ENABLE_SET (1 << 0)
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#define RETURN_STACK_ENABLE_SET (1 << 4)
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#define CPU_PF_BTBRMA_BIST 0x110C
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#define CPU_XC_CONFIG 0x1210
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#define XC_CONFIG_SUSP_ON_HLT (1 << 0)
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#define CPU_ID_CONFIG 0x1250
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#define ID_CONFIG_SERIAL_SET (1 << 0)
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#define CPU_AC_MSR 0x1301
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#define CPU_EX_BIST 0x1428
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@ -218,19 +206,16 @@
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#define RCONF_DEFAULT_LOWER_DEVRC_LOW_SHIFT 28
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#define RCONF_DEFAULT_LOWER_SYSTOP_SHIFT 8
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#define RCONF_DEFAULT_LOWER_SYSRC_SHIFT 0
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#define CPU_RCONF_BYPASS 0x180A
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#define CPU_RCONF_A0_BF 0x180B
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#define CPU_RCONF_C0_DF 0x180C
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#define CPU_RCONF_E0_FF 0x180D
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#define CPU_RCONF_SMM 0x180E
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#define RCONF_SMM_UPPER_SMMTOP_SHIFT 12
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#define RCONF_SMM_UPPER_RCSMM_SHIFT 0
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#define RCONF_SMM_LOWER_SMMBASE_SHIFT 12
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#define RCONF_SMM_LOWER_RCNORM_SHIFT 0
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#define RCONF_SMM_LOWER_EN_SET (1<<8)
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#define CPU_RCONF_DMM 0x180F
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#define RCONF_DMM_UPPER_DMMTOP_SHIFT 12
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#define RCONF_DMM_UPPER_RCDMM_SHIFT 0
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@ -264,7 +249,8 @@
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#define CPU_L2TB_ENTRY 0x189E
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#define CPU_L2TB_ENTRY_I 0x189F
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#define CPU_DM_BIST 0x18C0
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/* SMM */
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/* SMM */
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#define CPU_AC_SMM_CTL 0x1301
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#define SMM_NMI_EN_SET (1<<0)
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#define SMM_SUSP_EN_SET (1<<1)
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@ -308,16 +294,13 @@
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#define RSTPLL_UPPER_MDIV_SHIFT 9
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#define RSTPLL_UPPER_VDIV_SHIFT 6
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#define RSTPLL_UPPER_FBDIV_SHIFT 0
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#define RSTPLL_LOWER_SWFLAGS_SHIFT 26
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#define RSTPLL_LOWER_SWFLAGS_MASK (0x3F<<RSTPLL_LOWER_SWFLAGS_SHIFT)
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#define RSTPPL_LOWER_HOLD_COUNT_SHIFT 16
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#define RSTPPL_LOWER_BYPASS_SHIFT 15
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#define RSTPPL_LOWER_TST_SHIFT 11
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#define RSTPPL_LOWER_SDRMODE_SHIFT 10
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#define RSTPPL_LOWER_BOOTSTRAP_SHIFT 4
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#define RSTPPL_LOWER_LOCK_SET (1<<25)
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#define RSTPPL_LOWER_LOCKWAIT_SET (1<<24)
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#define RSTPPL_LOWER_BYPASS_SET (1<<15)
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@ -464,27 +447,27 @@
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#define DMM_OFFSET 0x0C0000000
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#define DMM_SIZE 128
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#define FB_OFFSET 0x41000000
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#define PCI_MEM_TOP 0x0EFFFFFFF // Top of PCI mem allocation region
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#define PCI_IO_TOP 0x0EFFF // Top of PCI I/O allocation region
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#define END_OPTIONROM_SPACE 0x0DFFF // E0000 is reserved for SystemROMs.
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#define PCI_MEM_TOP 0x0EFFFFFFF /* Top of PCI mem allocation region */
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#define PCI_IO_TOP 0x0EFFF /* Top of PCI I/O allocation region */
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#define END_OPTIONROM_SPACE 0x0DFFF /* E0000 is reserved for SystemROMs */
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#define MDD_SMBUS 0x06000 // SMBUS IO location
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#define MDD_GPIO 0x06100 // GPIO & ICF IO location
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#define MDD_MFGPT 0x06200 // General Purpose Timers IO location
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#define MDD_IRQ_MAPPER 0x06300 // IRQ Mapper
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#define ACPI_BASE 0x09C00 // ACPI Base
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#define MDD_PM 0x09D00 // Power Management Logic - placed at the end of ACPI
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#define MDD_SMBUS 0x06000 /* SMBUS IO location */
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#define MDD_GPIO 0x06100 /* GPIO & ICF IO location */
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#define MDD_MFGPT 0x06200 /* General Purpose Timers IO location */
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#define MDD_IRQ_MAPPER 0x06300 /* IRQ Mapper */
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#define ACPI_BASE 0x09C00 /* ACPI Base */
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#define MDD_PM 0x09D00 /* Power Management Logic - placed at the end of ACPI */
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#define CS5535_IDSEL 0x02000000 // IDSEL = AD25, device #15
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#define CS5535_IDSEL 0x02000000 /* IDSEL = AD25, device #15 */
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#define CHIPSET_DEV_NUM 15
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#define IDSEL_BASE 11 // bit 11 = device 1
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#define IDSEL_BASE 11 /* bit 11 = device 1 */
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/* SB LBAR IO + MEMORY MAP */
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#define SMBUS_BASE ( 0x6000)
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#define GPIO_BASE ( 0x6100)
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#define MFGPT_BASE ( 0x6200)
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#define IRQMAP_BASE ( 0x6300)
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#define PMLogic_BASE ( 0x9D00)
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#define SMBUS_BASE (0x6000)
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#define GPIO_BASE (0x6100)
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#define MFGPT_BASE (0x6200)
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#define IRQMAP_BASE (0x6300)
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#define PMLogic_BASE (0x9D00)
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#if !defined(__ROMCC__) && !defined(ASSEMBLY)
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@ -5,13 +5,10 @@
|
|||
#include "chip.h"
|
||||
#include "northbridge.h"
|
||||
|
||||
// FIXME handle UMA properly.
|
||||
#define VIDEO_MB 8 // MB of video memory
|
||||
/* FIXME handle UMA properly. */
|
||||
#define VIDEO_MB 8 /* MB of video memory */
|
||||
|
||||
|
||||
/*
|
||||
* This function mirrors the Graphics_Init routine in GeodeROM.
|
||||
*/
|
||||
/* This function mirrors the Graphics_Init routine in GeodeROM. */
|
||||
void graphics_init(void)
|
||||
{
|
||||
/* SoftVG initialization */
|
||||
|
|
|
|||
|
|
@ -22,13 +22,13 @@
|
|||
/* todo: add a resource record. We don't do this here because this may be called when
|
||||
* very little of the platform is actually working.
|
||||
*/
|
||||
int
|
||||
sizeram(void)
|
||||
int sizeram(void)
|
||||
{
|
||||
msr_t msr;
|
||||
int sizem = 0;
|
||||
unsigned short dimm;
|
||||
|
||||
/* Get the RAM size from the memory controller as calculated and set by auto_size_dimm() */
|
||||
msr = rdmsr(0x20000018);
|
||||
printk(BIOS_DEBUG, "sizeram: %08x:%08x\n", msr.hi, msr.lo);
|
||||
|
||||
|
|
@ -38,8 +38,7 @@ sizeram(void)
|
|||
if ((dimm & 7) != 7)
|
||||
sizem = (1 << ((dimm >> 12)-1)) * 8;
|
||||
|
||||
|
||||
/* dimm 1*/
|
||||
/* dimm 1 */
|
||||
dimm = msr.hi >> 16;
|
||||
/* installed? */
|
||||
if ((dimm & 7) != 7)
|
||||
|
|
@ -49,8 +48,7 @@ sizeram(void)
|
|||
return sizem;
|
||||
}
|
||||
|
||||
|
||||
/* here is programming for the various MSRs.*/
|
||||
/* here is programming for the various MSRs. */
|
||||
#define IM_QWAIT 0x100000
|
||||
|
||||
#define DMCF_WRITE_SERIALIZE_REQUEST (2<<12) /* 2 outstanding */ /* in high */
|
||||
|
|
@ -86,9 +84,8 @@ sizeram(void)
|
|||
#define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}}
|
||||
#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}}
|
||||
|
||||
|
||||
|
||||
struct msr_defaults {
|
||||
struct msr_defaults
|
||||
{
|
||||
int msr_no;
|
||||
msr_t msr;
|
||||
} msr_defaults [] = {
|
||||
|
|
@ -121,7 +118,8 @@ struct msr_defaults {
|
|||
};
|
||||
|
||||
/* note that dev is NOT used -- yet */
|
||||
static void irq_init_steering(struct device *dev, u16 irq_map) {
|
||||
static void irq_init_steering(struct device *dev, u16 irq_map)
|
||||
{
|
||||
/* Set up IRQ steering */
|
||||
u32 pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
|
||||
|
||||
|
|
@ -142,16 +140,12 @@ static void irq_init_steering(struct device *dev, u16 irq_map) {
|
|||
outl(irq_map, 0xCFC);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* setup_gx2_cache
|
||||
/* setup_gx2_cache
|
||||
*
|
||||
* Returns the amount of memory (in KB) available to the system. This is the
|
||||
* total amount of memory less the amount of memory reserved for SMM use.
|
||||
*
|
||||
*/
|
||||
static int
|
||||
setup_gx2_cache(void)
|
||||
static int setup_gx2_cache(void)
|
||||
{
|
||||
msr_t msr;
|
||||
unsigned long long val;
|
||||
|
|
@ -164,7 +158,7 @@ setup_gx2_cache(void)
|
|||
/* set romrp */
|
||||
val = ((unsigned long long) ROM_PROPERTIES) << 56;
|
||||
/* make rom base useful for 1M roms */
|
||||
/* Flash base address -- sized for 1M for now*/
|
||||
/* Flash base address -- sized for 1M for now */
|
||||
val |= ((unsigned long long) 0xfff00)<<36;
|
||||
/* set the devrp properties */
|
||||
val |= ((unsigned long long) DEVICE_PROPERTIES) << 28;
|
||||
|
|
@ -172,7 +166,7 @@ setup_gx2_cache(void)
|
|||
/* yank off memory for the SMM handler */
|
||||
sizekbytes -= SMM_SIZE;
|
||||
sizereg = sizekbytes;
|
||||
sizereg *= 1024; // convert to bytes
|
||||
sizereg *= 1024; /* convert to bytes */
|
||||
sizereg >>= 12;
|
||||
sizereg <<= 8;
|
||||
val |= sizereg;
|
||||
|
|
@ -188,10 +182,8 @@ setup_gx2_cache(void)
|
|||
}
|
||||
|
||||
/* we have to do this here. We have not found a nicer way to do it */
|
||||
static void
|
||||
setup_gx2(void)
|
||||
static void setup_gx2(void)
|
||||
{
|
||||
|
||||
unsigned long tmp, tmp2;
|
||||
msr_t msr;
|
||||
unsigned long size_kb, membytes;
|
||||
|
|
@ -205,8 +197,8 @@ setup_gx2(void)
|
|||
*/
|
||||
|
||||
/* we need to set 0x10000028 and 0x40000029 */
|
||||
/*
|
||||
* These two descriptors cover the range from 1 MB (0x100000) to
|
||||
|
||||
/* These two descriptors cover the range from 1 MB (0x100000) to
|
||||
* SYSTOP (a.k.a. TOM, or Top of Memory)
|
||||
*/
|
||||
|
||||
|
|
@ -258,11 +250,11 @@ setup_gx2(void)
|
|||
msr = rdmsr(0x1808);
|
||||
printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo);
|
||||
#endif
|
||||
#if 0 // SDG - don't do this
|
||||
#if 0 /* SDG - don't do this */
|
||||
/* now do the default MSR values */
|
||||
for(i = 0; msr_defaults[i].msr_no; i++) {
|
||||
msr_t msr;
|
||||
wrmsr(msr_defaults[i].msr_no, msr_defaults[i].msr); // MSR - see table above
|
||||
wrmsr(msr_defaults[i].msr_no, msr_defaults[i].msr); /* MSR - see table above */
|
||||
msr = rdmsr(msr_defaults[i].msr_no);
|
||||
printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", msr_defaults[i].msr_no, msr.hi,msr.lo);
|
||||
}
|
||||
|
|
@ -330,8 +322,6 @@ static void set_resources(struct device *dev)
|
|||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
||||
static struct device_operations northbridge_operations = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
#if 0
|
||||
|
|
@ -350,7 +340,7 @@ static const struct pci_driver northbridge_driver __pci_driver = {
|
|||
.device = PCI_DEVICE_ID_NS_GX2,
|
||||
};
|
||||
|
||||
// FIXME handle UMA correctly.
|
||||
/* FIXME handle UMA correctly. */
|
||||
#define FRAMEBUFFERK 4096
|
||||
|
||||
static void pci_domain_set_resources(device_t dev)
|
||||
|
|
|
|||
|
|
@ -15,7 +15,8 @@
|
|||
|
||||
/* put this here for now, we are not sure where it belongs */
|
||||
|
||||
struct gliutable {
|
||||
struct gliutable
|
||||
{
|
||||
unsigned long desc_name;
|
||||
unsigned short desc_type;
|
||||
unsigned long hi, lo;
|
||||
|
|
@ -46,7 +47,8 @@ struct gliutable gliu1table[] = {
|
|||
|
||||
struct gliutable *gliutables[] = {gliu0table, gliu1table, 0};
|
||||
|
||||
struct msrinit {
|
||||
struct msrinit
|
||||
{
|
||||
unsigned long msrnum;
|
||||
msr_t msr;
|
||||
};
|
||||
|
|
@ -64,7 +66,8 @@ struct msrinit ClockGatingDefault [] = {
|
|||
{FG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* Always on */
|
||||
{0xffffffff, {0xffffffff, 0xffffffff}},
|
||||
};
|
||||
/* All On */
|
||||
|
||||
/* All On */
|
||||
struct msrinit ClockGatingAllOn[] = {
|
||||
{GLIU0_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}},
|
||||
{MC_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}},
|
||||
|
|
@ -78,16 +81,16 @@ struct msrinit ClockGatingAllOn[] = {
|
|||
{0xffffffff, {0xffffffff, 0xffffffff}},
|
||||
};
|
||||
|
||||
/* Performance */
|
||||
/* Performance */
|
||||
struct msrinit ClockGatingPerformance[] = {
|
||||
{VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163*/
|
||||
{VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163 */
|
||||
{GP_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}},
|
||||
{DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0155}},
|
||||
{GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}},
|
||||
{0xffffffff, {0xffffffff, 0xffffffff}},
|
||||
};
|
||||
|
||||
/* SET GeodeLink PRIORITY */
|
||||
/* SET GeodeLink PRIORITY */
|
||||
struct msrinit GeodeLinkPriorityTable [] = {
|
||||
{CPU_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0220}}, /* CPU Priority. */
|
||||
{DF_GLD_MSR_MASTER_CONF, {.hi=0x00,.lo=0x0000}}, /* DF Priority. */
|
||||
|
|
@ -103,8 +106,8 @@ struct msrinit GeodeLinkPriorityTable [] = {
|
|||
/* do we have dmi or not? assume NO per AMD */
|
||||
int havedmi = 0;
|
||||
|
||||
static void
|
||||
writeglmsr(struct gliutable *gl){
|
||||
static void writeglmsr(struct gliutable *gl)
|
||||
{
|
||||
msr_t msr;
|
||||
|
||||
msr.lo = gl->lo;
|
||||
|
|
@ -116,8 +119,7 @@ writeglmsr(struct gliutable *gl){
|
|||
printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
static void
|
||||
ShadowInit(struct gliutable *gl)
|
||||
static void ShadowInit(struct gliutable *gl)
|
||||
{
|
||||
msr_t msr;
|
||||
|
||||
|
|
@ -132,14 +134,12 @@ ShadowInit(struct gliutable *gl)
|
|||
* CLEAN ME UP
|
||||
*/
|
||||
/* yes, this duplicates later code, but it seems that is how they want it done. */
|
||||
static void
|
||||
SysmemInit(struct gliutable *gl)
|
||||
static void SysmemInit(struct gliutable *gl)
|
||||
{
|
||||
msr_t msr;
|
||||
int sizembytes, sizebytes;
|
||||
|
||||
/*
|
||||
* Figure out how much RAM is in the machine and alocate all to the
|
||||
/* Figure out how much RAM is in the machine and alocate all to the
|
||||
* system. We will adjust for SMM and DMM now and Frame Buffer later.
|
||||
*/
|
||||
sizembytes = sizeram();
|
||||
|
|
@ -164,8 +164,8 @@ SysmemInit(struct gliutable *gl)
|
|||
gl->desc_name, msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
static void
|
||||
DMMGL0Init(struct gliutable *gl) {
|
||||
static void DMMGL0Init(struct gliutable *gl)
|
||||
{
|
||||
msr_t msr;
|
||||
int sizebytes = sizeram()<<20;
|
||||
long offset;
|
||||
|
|
@ -191,8 +191,8 @@ DMMGL0Init(struct gliutable *gl) {
|
|||
printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
static void
|
||||
DMMGL1Init(struct gliutable *gl) {
|
||||
static void DMMGL1Init(struct gliutable *gl)
|
||||
{
|
||||
msr_t msr;
|
||||
|
||||
if (! havedmi)
|
||||
|
|
@ -214,8 +214,8 @@ DMMGL1Init(struct gliutable *gl) {
|
|||
printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
static void
|
||||
SMMGL0Init(struct gliutable *gl) {
|
||||
static void SMMGL0Init(struct gliutable *gl)
|
||||
{
|
||||
msr_t msr;
|
||||
int sizebytes = sizeram()<<20;
|
||||
long offset;
|
||||
|
|
@ -242,8 +242,8 @@ SMMGL0Init(struct gliutable *gl) {
|
|||
printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
static void
|
||||
SMMGL1Init(struct gliutable *gl) {
|
||||
static void SMMGL1Init(struct gliutable *gl)
|
||||
{
|
||||
msr_t msr;
|
||||
printk(BIOS_DEBUG, "%s:\n", __func__ );
|
||||
|
||||
|
|
@ -259,9 +259,8 @@ SMMGL1Init(struct gliutable *gl) {
|
|||
printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
static void
|
||||
GLIUInit(struct gliutable *gl){
|
||||
|
||||
static void GLIUInit(struct gliutable *gl)
|
||||
{
|
||||
while (gl->desc_type != GL_END){
|
||||
switch(gl->desc_type){
|
||||
default:
|
||||
|
|
@ -295,8 +294,7 @@ GLIUInit(struct gliutable *gl){
|
|||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Set up GLPCI settings for reads/write into memory.
|
||||
/* Set up GLPCI settings for reads/write into memory.
|
||||
*
|
||||
* R0: 0-640KB,
|
||||
* R1: 1MB - Top of System Memory
|
||||
|
|
@ -304,7 +302,8 @@ GLIUInit(struct gliutable *gl){
|
|||
* R3: Framebuffer? - not set up yet
|
||||
* R4: ??
|
||||
*/
|
||||
static void GLPCIInit(void){
|
||||
static void GLPCIInit(void)
|
||||
{
|
||||
struct gliutable *gl = 0;
|
||||
int i;
|
||||
msr_t msr;
|
||||
|
|
@ -334,7 +333,7 @@ static void GLPCIInit(void){
|
|||
* base of 1M and top of around 256M
|
||||
*/
|
||||
/* we have to create a page-aligned (4KB page) address for base and top
|
||||
* So we need a high page aligned addresss (pah) and low page aligned address (pal)
|
||||
* so we need a high page aligned addresss (pah) and low page aligned address (pal)
|
||||
* pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12
|
||||
*/
|
||||
printk(BIOS_DEBUG, "GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
|
||||
|
|
@ -504,8 +503,7 @@ static void GeodeLinkPriority(void)
|
|||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Get the GLIU0 shadow register settings.
|
||||
/* Get the GLIU0 shadow register settings.
|
||||
*
|
||||
* If the setShadow function is used then all shadow descriptors
|
||||
* will stay sync'ed.
|
||||
|
|
@ -517,8 +515,7 @@ static uint64_t getShadow(void)
|
|||
return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set the cache RConf registers for the memory hole.
|
||||
/* Set the cache RConf registers for the memory hole.
|
||||
*
|
||||
* Keeps all cache shadow descriptors sync'ed.
|
||||
* This is part of the PCI lockup solution.
|
||||
|
|
@ -572,8 +569,7 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)
|
|||
wrmsr(CPU_RCONF_E0_FF, msr);
|
||||
}
|
||||
|
||||
/*
|
||||
* Set the GLPCI registers for the memory hole.
|
||||
/* Set the GLPCI registers for the memory hole.
|
||||
* Keeps all cache shadow descriptors sync'ed.
|
||||
* Entry: EDX:EAX is the shadow settings
|
||||
*/
|
||||
|
|
@ -588,8 +584,7 @@ static void setShadowGLPCI(uint32_t shadowHi, uint32_t shadowLo)
|
|||
wrmsr(GLPCI_REN, msr);
|
||||
}
|
||||
|
||||
/*
|
||||
* Set the GLIU SC register settings. Scans descriptor tables for SC_SHADOW.
|
||||
/* Set the GLIU SC register settings. Scans descriptor tables for SC_SHADOW.
|
||||
* Keeps all shadow descriptors sync'ed.
|
||||
* Entry: EDX:EAX is the shadow settings
|
||||
*/
|
||||
|
|
@ -630,8 +625,7 @@ static void shadowRom(void)
|
|||
setShadow(shadowSettings);
|
||||
}
|
||||
|
||||
/*
|
||||
* Set up RCONF_DEFAULT and any other RCONF registers needed.
|
||||
/* Set up RCONF_DEFAULT and any other RCONF registers needed.
|
||||
*
|
||||
* DEVRC_RCONF_DEFAULT:
|
||||
* ROMRC(63:56) = 04h ; write protect ROMBASE
|
||||
|
|
@ -645,8 +639,7 @@ static void shadowRom(void)
|
|||
#define ROMBASE_RCONF_DEFAULT 0xFFFC0000
|
||||
#define ROMRC_RCONF_DEFAULT 0x25
|
||||
|
||||
static void
|
||||
RCONFInit(void)
|
||||
static void RCONFInit(void)
|
||||
{
|
||||
struct gliutable *gl = 0;
|
||||
int i;
|
||||
|
|
|
|||
Loading…
Reference in New Issue