soc/mediatek/mt8173: Remove dual DSI mode
The 'dual DSI mode' was never used by any real boards running coreboot and is introducing lots of complexity when it comes to refactoring. In order to create a common display stack for MTK SOCs, we want to first drop dual DSI mode so 8173 and 8183 DSI/DDP implementation will be more similar to each other. BUG=b:80501386,b:117254947 TEST=emerge-oak coreboot Change-Id: I357c30cc687803ca8045d0b055dec2e22eef4291 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34693 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Hung-Te Lin
Julius Werner
parent
ca38fbcdbf
commit
1c6e5a6e9d
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@ -226,25 +226,21 @@ static void display_startup(void)
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struct edid edid;
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int ret;
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u32 mipi_dsi_flags;
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bool dual_dsi_mode;
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if (read_edid_from_ps8640(&edid) < 0)
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return;
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dual_dsi_mode = false;
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mipi_dsi_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
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edid_set_framebuffer_bits_per_pixel(&edid, 32, 0);
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mtk_ddp_init(dual_dsi_mode);
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ret = mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4,
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dual_dsi_mode, &edid);
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mtk_ddp_init();
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ret = mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, &edid);
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if (ret < 0) {
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printk(BIOS_ERR, "dsi init fail\n");
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return;
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}
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mtk_ddp_mode_set(&edid, dual_dsi_mode);
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mtk_ddp_mode_set(&edid);
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set_vbe_mode_info_valid(&edid, (uintptr_t)0);
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}
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@ -24,23 +24,14 @@
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#define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16)
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#define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16)
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static void disp_config_main_path_connection(bool dual_dsi_mode)
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static void disp_config_main_path_connection(void)
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{
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write32(&mmsys_cfg->disp_ovl0_mout_en, OVL0_MOUT_EN_COLOR0);
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write32(&mmsys_cfg->disp_color0_sel_in, COLOR0_SEL_IN_OVL0);
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write32(&mmsys_cfg->disp_od_mout_en, OD_MOUT_EN_RDMA0);
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if (dual_dsi_mode) {
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write32(&mmsys_cfg->disp_ufoe_mout_en, UFOE_MOUT_EN_SPLIT1);
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write32(&mmsys_cfg->dsi0_sel_in, DSI0_SEL_IN_SPLIT1);
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write32(&mmsys_cfg->dsi1_sel_in, DSI1_SEL_IN_SPLIT1);
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} else {
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write32(&mmsys_cfg->disp_ufoe_mout_en, UFOE_MOUT_EN_DSI0);
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write32(&mmsys_cfg->dsi0_sel_in, DSI0_SEL_IN_UFOE);
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}
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}
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static void disp_config_main_path_mutex(void)
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{
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@ -105,16 +96,10 @@ static void od_start(u32 width, u32 height)
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write32(&disp_od->en, 1);
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}
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static void ufoe_start(u32 width, u32 height, bool dual_dsi_mode)
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static void ufoe_start(u32 width, u32 height)
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{
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if (dual_dsi_mode) {
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write32(&disp_ufoe->frame_width, width);
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write32(&disp_ufoe->frame_height, height);
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write32(&disp_ufoe->start, UFO_LR);
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} else {
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write32(&disp_ufoe->start, UFO_BYPASS);
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}
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}
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static void color_start(u32 width, u32 height)
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{
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@ -124,11 +109,6 @@ static void color_start(u32 width, u32 height)
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write32(&disp_color[0]->start, BIT(0));
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}
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static void split_start(void)
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{
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write32(&disp_split->start, 1);
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}
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static void ovl_layer_config(u32 fmt, u32 bpp, u32 width, u32 height)
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{
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write32(&disp_ovl[0]->layer[0].con, fmt << 12);
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@ -138,8 +118,7 @@ static void ovl_layer_config(u32 fmt, u32 bpp, u32 width, u32 height)
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ovl_layer_enable();
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}
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static void main_disp_path_setup(u32 width, u32 height, u32 pixel_clk,
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bool dual_dsi_mode)
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static void main_disp_path_setup(u32 width, u32 height, u32 pixel_clk)
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{
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/* Setup OVL */
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ovl_set_roi(width, height, 0);
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@ -151,34 +130,20 @@ static void main_disp_path_setup(u32 width, u32 height, u32 pixel_clk,
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od_start(width, height);
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/* Setup UFOE */
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ufoe_start(width, height, dual_dsi_mode);
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if (dual_dsi_mode)
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split_start();
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ufoe_start(width, height);
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/* Setup Color */
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color_start(width, height);
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/* Setup main path connection */
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disp_config_main_path_connection(dual_dsi_mode);
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disp_config_main_path_connection();
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/* Setup main path mutex */
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disp_config_main_path_mutex();
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}
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static void disp_clock_on(bool dual_dsi_mode)
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static void disp_clock_on(void)
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{
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u32 dual_dsi_cg_con0;
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u32 dual_dsi_cg_con1;
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if (dual_dsi_mode) {
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dual_dsi_cg_con0 = CG_CON0_DISP_SPLIT1;
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dual_dsi_cg_con1 = CG_CON1_DSI1_ENGINE | CG_CON1_DSI1_DIGITAL;
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} else {
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dual_dsi_cg_con0 = 0;
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dual_dsi_cg_con1 = 0;
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}
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clrbits_le32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_SMI_COMMON |
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CG_CON0_SMI_LARB0 |
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CG_CON0_MUTEX_32K |
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@ -186,26 +151,24 @@ static void disp_clock_on(bool dual_dsi_mode)
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CG_CON0_DISP_RDMA0 |
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CG_CON0_DISP_COLOR0 |
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CG_CON0_DISP_UFOE |
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dual_dsi_cg_con0 |
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CG_CON0_DISP_OD);
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clrbits_le32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DSI0_ENGINE |
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CG_CON1_DSI0_DIGITAL |
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dual_dsi_cg_con1);
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CG_CON1_DSI0_DIGITAL);
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}
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void mtk_ddp_init(bool dual_dsi_mode)
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void mtk_ddp_init(void)
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{
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disp_clock_on(dual_dsi_mode);
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disp_clock_on();
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}
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void mtk_ddp_mode_set(const struct edid *edid, bool dual_dsi_mode)
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void mtk_ddp_mode_set(const struct edid *edid)
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{
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u32 fmt = OVL_INFMT_RGBA8888;
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u32 bpp = edid->framebuffer_bits_per_pixel / 8;
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main_disp_path_setup(edid->mode.ha, edid->mode.va,
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edid->mode.pixel_clock, dual_dsi_mode);
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edid->mode.pixel_clock);
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rdma_start();
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@ -17,78 +17,9 @@
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#include <console/console.h>
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#include <delay.h>
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#include <soc/addressmap.h>
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#include <soc/i2c.h>
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#include <soc/gpio.h>
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#include <soc/dsi.h>
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#include <soc/ddp.h>
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#include <timer.h>
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static bool dual_dsi_mode;
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static void mipi_write32(void *a, uint32_t v)
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{
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void *a1 = a + (MIPI_TX1_BASE - MIPI_TX0_BASE);
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write32(a, v);
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if (dual_dsi_mode)
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write32(a1, v);
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}
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static void mipi_clrsetbits_le32(void *a, uint32_t m, uint32_t v)
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{
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void *a1 = a + (MIPI_TX1_BASE - MIPI_TX0_BASE);
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clrsetbits_le32(a, m, v);
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if (dual_dsi_mode)
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clrsetbits_le32(a1, m, v);
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}
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static void mipi_clrbits_le32(void *a, uint32_t m)
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{
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void *a1 = a + (MIPI_TX1_BASE - MIPI_TX0_BASE);
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clrbits_le32(a, m);
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if (dual_dsi_mode)
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clrbits_le32(a1, m);
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}
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static void mipi_setbits_le32(void *a, uint32_t m)
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{
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void *a1 = a + (MIPI_TX1_BASE - MIPI_TX0_BASE);
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setbits_le32(a, m);
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if (dual_dsi_mode)
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setbits_le32(a1, m);
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}
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static void dsi_write32(void *a, uint32_t v)
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{
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void *a1 = a + (DSI1_BASE - DSI0_BASE);
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write32(a, v);
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if (dual_dsi_mode)
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write32(a1, v);
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}
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static void dsi_clrsetbits_le32(void *a, uint32_t m, uint32_t v)
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{
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void *a1 = a + (DSI1_BASE - DSI0_BASE);
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clrsetbits_le32(a, m, v);
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if (dual_dsi_mode)
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clrsetbits_le32(a1, m, v);
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}
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static void dsi_clrbits_le32(void *a, uint32_t m)
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{
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void *a1 = a + (DSI1_BASE - DSI0_BASE);
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clrbits_le32(a, m);
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if (dual_dsi_mode)
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clrbits_le32(a1, m);
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}
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static void dsi_setbits_le32(void *a, uint32_t m)
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{
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void *a1 = a + (DSI1_BASE - DSI0_BASE);
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setbits_le32(a, m);
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if (dual_dsi_mode)
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setbits_le32(a1, m);
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}
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static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes,
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const struct edid *edid)
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{
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@ -108,19 +39,19 @@ static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes,
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reg = (reg & (~RG_DSI_V12_SEL)) | (4 << 5);
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reg |= RG_DSI_BG_CKEN;
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reg |= RG_DSI_BG_CORE_EN;
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mipi_write32(&mipi_tx0->dsi_bg_con, reg);
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write32(&mipi_tx0->dsi_bg_con, reg);
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udelay(30);
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mipi_clrsetbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_LNT_IMP_CAL_CODE,
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clrsetbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_LNT_IMP_CAL_CODE,
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8 << 4 | RG_DSI_LNT_HS_BIAS_EN);
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mipi_setbits_le32(&mipi_tx0->dsi_con,
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setbits_le32(&mipi_tx0->dsi_con,
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RG_DSI0_CKG_LDOOUT_EN | RG_DSI0_LDOCORE_EN);
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mipi_clrsetbits_le32(&mipi_tx0->dsi_pll_pwr, RG_DSI_MPPLL_SDM_ISO_EN,
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clrsetbits_le32(&mipi_tx0->dsi_pll_pwr, RG_DSI_MPPLL_SDM_ISO_EN,
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RG_DSI_MPPLL_SDM_PWR_ON);
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mipi_clrbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN);
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clrbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN);
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switch (format) {
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case MIPI_DSI_FMT_RGB565:
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@ -146,8 +77,6 @@ static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes,
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data_rate = edid->mode.pixel_clock * 102 * bit_per_pixel /
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(lanes * 1000 * 100);
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mipi_tx_rate = data_rate;
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if (dual_dsi_mode)
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data_rate /= 2;
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if (data_rate > 500) {
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txdiv0 = 0;
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@ -171,7 +100,7 @@ static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes,
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return -1;
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}
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mipi_clrsetbits_le32(&mipi_tx0->dsi_pll_con0,
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clrsetbits_le32(&mipi_tx0->dsi_pll_con0,
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RG_DSI0_MPPLL_TXDIV1 | RG_DSI0_MPPLL_TXDIV0 |
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RG_DSI0_MPPLL_PREDIV, txdiv1 << 5 | txdiv0 << 3);
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@ -185,21 +114,21 @@ static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes,
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*/
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pcw = (u64)(data_rate * (1 << txdiv0) * (1 << txdiv1)) << 24;
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pcw /= 13;
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mipi_write32(&mipi_tx0->dsi_pll_con2, pcw);
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write32(&mipi_tx0->dsi_pll_con2, pcw);
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mipi_setbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_FRA_EN);
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setbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_FRA_EN);
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mipi_setbits_le32(&mipi_tx0->dsi_clock_lane, LDOOUT_EN);
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setbits_le32(&mipi_tx0->dsi_clock_lane, LDOOUT_EN);
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for (i = 0; i < lanes; i++)
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mipi_setbits_le32(&mipi_tx0->dsi_data_lane[i], LDOOUT_EN);
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setbits_le32(&mipi_tx0->dsi_data_lane[i], LDOOUT_EN);
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mipi_setbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN);
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setbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN);
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udelay(40);
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mipi_clrbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_SSC_EN);
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mipi_clrbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_PAD_TIE_LOW_EN);
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clrbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_SSC_EN);
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clrbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_PAD_TIE_LOW_EN);
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return mipi_tx_rate;
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}
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@ -222,26 +151,26 @@ static void mtk_dsi_phy_timconfig(u32 data_rate)
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DIV_ROUND_UP(80 + 52 * ui, cycle_time) << 8 |
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DIV_ROUND_UP(0x40, cycle_time);
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dsi_write32(&dsi0->dsi_phy_timecon0, timcon0);
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dsi_write32(&dsi0->dsi_phy_timecon1, timcon1);
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dsi_write32(&dsi0->dsi_phy_timecon2, timcon2);
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dsi_write32(&dsi0->dsi_phy_timecon3, timcon3);
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write32(&dsi0->dsi_phy_timecon0, timcon0);
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write32(&dsi0->dsi_phy_timecon1, timcon1);
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write32(&dsi0->dsi_phy_timecon2, timcon2);
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write32(&dsi0->dsi_phy_timecon3, timcon3);
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}
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static void mtk_dsi_reset(void)
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{
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dsi_setbits_le32(&dsi0->dsi_con_ctrl, 3);
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dsi_clrbits_le32(&dsi0->dsi_con_ctrl, 1);
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setbits_le32(&dsi0->dsi_con_ctrl, 3);
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clrbits_le32(&dsi0->dsi_con_ctrl, 1);
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}
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static void mtk_dsi_clk_hs_mode_enable(void)
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{
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dsi_setbits_le32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN);
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setbits_le32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN);
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}
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static void mtk_dsi_clk_hs_mode_disable(void)
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{
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dsi_clrbits_le32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN);
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clrbits_le32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN);
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}
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static void mtk_dsi_set_mode(u32 mode_flags)
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@ -258,7 +187,7 @@ static void mtk_dsi_set_mode(u32 mode_flags)
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tmp_reg1 = SYNC_PULSE_MODE;
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}
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dsi_write32(&dsi0->dsi_mode_ctrl, tmp_reg1);
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write32(&dsi0->dsi_mode_ctrl, tmp_reg1);
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}
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static void mtk_dsi_rxtx_control(u32 mode_flags, u32 lanes)
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@ -284,7 +213,7 @@ static void mtk_dsi_rxtx_control(u32 mode_flags, u32 lanes)
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tmp_reg |= (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6;
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tmp_reg |= (mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3;
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dsi_write32(&dsi0->dsi_txrx_ctrl, tmp_reg);
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write32(&dsi0->dsi_txrx_ctrl, tmp_reg);
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}
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static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format,
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@ -308,10 +237,10 @@ static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format,
|
|||
edid->mode.vborder;
|
||||
vfp_byte = edid->mode.vso - edid->mode.vborder;
|
||||
|
||||
dsi_write32(&dsi0->dsi_vsa_nl, edid->mode.vspw);
|
||||
dsi_write32(&dsi0->dsi_vbp_nl, vbp_byte);
|
||||
dsi_write32(&dsi0->dsi_vfp_nl, vfp_byte);
|
||||
dsi_write32(&dsi0->dsi_vact_nl, edid->mode.va);
|
||||
write32(&dsi0->dsi_vsa_nl, edid->mode.vspw);
|
||||
write32(&dsi0->dsi_vbp_nl, vbp_byte);
|
||||
write32(&dsi0->dsi_vfp_nl, vfp_byte);
|
||||
write32(&dsi0->dsi_vact_nl, edid->mode.va);
|
||||
|
||||
if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
|
||||
hbp_byte = (edid->mode.hbl - edid->mode.hso - edid->mode.hspw -
|
||||
|
|
@ -323,9 +252,9 @@ static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format,
|
|||
hsync_active_byte = edid->mode.hspw * bpp - 10;
|
||||
hfp_byte = (edid->mode.hso - edid->mode.hborder) * bpp - 12;
|
||||
|
||||
dsi_write32(&dsi0->dsi_hsa_wc, hsync_active_byte);
|
||||
dsi_write32(&dsi0->dsi_hbp_wc, hbp_byte);
|
||||
dsi_write32(&dsi0->dsi_hfp_wc, hfp_byte);
|
||||
write32(&dsi0->dsi_hsa_wc, hsync_active_byte);
|
||||
write32(&dsi0->dsi_hbp_wc, hbp_byte);
|
||||
write32(&dsi0->dsi_hfp_wc, hfp_byte);
|
||||
|
||||
switch (format) {
|
||||
case MIPI_DSI_FMT_RGB888:
|
||||
|
|
@ -346,60 +275,22 @@ static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format,
|
|||
}
|
||||
|
||||
hactive = edid->mode.ha;
|
||||
if (dual_dsi_mode)
|
||||
hactive /= 2;
|
||||
packet_fmt |= (hactive * bpp) & DSI_PS_WC;
|
||||
|
||||
dsi_write32(&dsi0->dsi_psctrl, packet_fmt);
|
||||
write32(&dsi0->dsi_psctrl, packet_fmt);
|
||||
}
|
||||
|
||||
static void mtk_dsi_start(void)
|
||||
{
|
||||
dsi_write32(&dsi0->dsi_start, 0);
|
||||
write32(&dsi0->dsi_start, 0);
|
||||
/* Only start master DSI */
|
||||
write32(&dsi0->dsi_start, 1);
|
||||
}
|
||||
|
||||
static void mtk_dsi_tx_cmd_type0(u8 cmd)
|
||||
{
|
||||
struct stopwatch sw;
|
||||
u32 cmdq0;
|
||||
u32 intsta_0, intsta_1;
|
||||
|
||||
cmdq0 = (MIPI_DSI_DCS_SHORT_WRITE << 8) | SHORT_PACKET | (cmd << 16);
|
||||
|
||||
dsi_write32(&dsi0->dsi_cmdq0, cmdq0);
|
||||
dsi_clrsetbits_le32(&dsi0->dsi_cmdq_size, CMDQ_SIZE, 1);
|
||||
dsi_write32(&dsi0->dsi_intsta, 0);
|
||||
|
||||
dsi_write32(&dsi0->dsi_start, 1);
|
||||
|
||||
stopwatch_init_usecs_expire(&sw, 400);
|
||||
do {
|
||||
intsta_0 = read32(&dsi0->dsi_intsta);
|
||||
intsta_1 = read32(&dsi1->dsi_intsta);
|
||||
if ((intsta_0 & CMD_DONE_INT_FLAG) &&
|
||||
(intsta_1 & CMD_DONE_INT_FLAG))
|
||||
break;
|
||||
udelay(4);
|
||||
} while (!stopwatch_expired(&sw));
|
||||
|
||||
if (!(intsta_0 & CMD_DONE_INT_FLAG))
|
||||
printk(BIOS_ERR, "DSI0 DONE INT Timeout\n");
|
||||
|
||||
if (!(intsta_1 & CMD_DONE_INT_FLAG))
|
||||
printk(BIOS_ERR, "DSI1 DONE INT Timeout\n");
|
||||
|
||||
dsi_write32(&dsi0->dsi_start, 0);
|
||||
}
|
||||
|
||||
int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, bool dual,
|
||||
const struct edid *edid)
|
||||
int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid)
|
||||
{
|
||||
int data_rate;
|
||||
|
||||
dual_dsi_mode = dual;
|
||||
|
||||
data_rate = mtk_dsi_phy_clk_setting(format, lanes, edid);
|
||||
|
||||
if (data_rate < 0)
|
||||
|
|
@ -413,21 +304,6 @@ int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, bool dual,
|
|||
mtk_dsi_set_mode(mode_flags);
|
||||
mtk_dsi_clk_hs_mode_enable();
|
||||
|
||||
if (dual_dsi_mode) {
|
||||
dsi_write32(&dsi0->dsi_start, 0);
|
||||
/* Disable dual_dsi when in CMD_MODE */
|
||||
dsi_write32(&dsi0->dsi_con_ctrl, DSI_EN);
|
||||
|
||||
dsi_write32(&dsi0->dsi_mode_ctrl, CMD_MODE);
|
||||
|
||||
mtk_dsi_tx_cmd_type0(MIPI_DCS_EXIT_SLEEP_MODE);
|
||||
mtk_dsi_tx_cmd_type0(MIPI_DCS_SET_DISPLAY_ON);
|
||||
|
||||
dsi_write32(&dsi0->dsi_con_ctrl, DSI_EN | DSI_DUAL);
|
||||
|
||||
dsi_write32(&dsi0->dsi_mode_ctrl, BURST_MODE);
|
||||
}
|
||||
|
||||
mtk_dsi_start();
|
||||
|
||||
return 0;
|
||||
|
|
@ -438,7 +314,7 @@ void mtk_dsi_pin_drv_ctrl(void)
|
|||
struct stopwatch sw;
|
||||
uint32_t pwr_ack;
|
||||
|
||||
mipi_setbits_le32(&lvds_tx1->vopll_ctl3, RG_DA_LVDSTX_PWR_ON);
|
||||
setbits_le32(&lvds_tx1->vopll_ctl3, RG_DA_LVDSTX_PWR_ON);
|
||||
|
||||
stopwatch_init_usecs_expire(&sw, 1000);
|
||||
|
||||
|
|
@ -448,10 +324,7 @@ void mtk_dsi_pin_drv_ctrl(void)
|
|||
return;
|
||||
}
|
||||
pwr_ack = read32(&lvds_tx1->vopll_ctl3) & RG_AD_LVDSTX_PWR_ACK;
|
||||
if (dual_dsi_mode)
|
||||
pwr_ack &= read32(&lvds_tx2->vopll_ctl3) &
|
||||
RG_AD_LVDSTX_PWR_ACK;
|
||||
} while (pwr_ack == 0);
|
||||
|
||||
mipi_clrbits_le32(&lvds_tx1->vopll_ctl3, RG_DA_LVDS_ISO_EN);
|
||||
clrbits_le32(&lvds_tx1->vopll_ctl3, RG_DA_LVDS_ISO_EN);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -407,12 +407,6 @@ enum {
|
|||
UFO_LR = BIT(3) | BIT(0),
|
||||
};
|
||||
|
||||
struct disp_split_regs {
|
||||
u32 start;
|
||||
};
|
||||
|
||||
static struct disp_split_regs *const disp_split = (void *)DISP_SPLIT1_BASE;
|
||||
|
||||
struct disp_color_regs {
|
||||
u8 reserved0[1024];
|
||||
u32 cfg_main;
|
||||
|
|
@ -452,7 +446,7 @@ enum OVL_INPUT_FORMAT {
|
|||
OVL_INFMT_ABGR8888 = OVL_INFMT_ARGB8888 + OVL_COLOR_BASE,
|
||||
};
|
||||
|
||||
void mtk_ddp_init(bool dual_dsi_mode);
|
||||
void mtk_ddp_mode_set(const struct edid *edid, bool dual_dsi_mode);
|
||||
void mtk_ddp_init(void);
|
||||
void mtk_ddp_mode_set(const struct edid *edid);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -443,7 +443,7 @@ enum {
|
|||
};
|
||||
|
||||
int mtk_dsi_init(u32 mode_flags, enum mipi_dsi_pixel_format format, u32 lanes,
|
||||
bool dual_dsi_mode, const struct edid *edid);
|
||||
const struct edid *edid);
|
||||
void mtk_dsi_pin_drv_ctrl(void);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue