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cpu/intel/haswell: Set C9/C10 vccmin 

Backport commit ab7586fa26 (broadwell: Set C9/C10 vccmin) to Haswell.

Change-Id: I9cddc7dd45e96c6f99327ee2583917bf8bedfbdd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46922
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-10-29 00:01:29 +01:00
parent c86b119495
commit 1c7ba62eb7
2 changed files with 26 additions and 0 deletions
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23
src/cpu/intel/haswell/haswell_init.c
View File

@ -226,6 +226,26 @@ static u32 pcode_mailbox_read(u32 command)
return MCHBAR32(BIOS_MAILBOX_DATA);
}
static int pcode_mailbox_write(u32 command, u32 data)
{
if (pcode_ready() < 0) {
printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n");
return -1;
}
MCHBAR32(BIOS_MAILBOX_DATA) = data;
/* Send command and start transaction */
MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY;
if (pcode_ready() < 0) {
printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n");
return -1;
}
return 0;
}
static void initialize_vr_config(void)
{
struct cpu_vr_config vr_config = { 0 };
@ -300,6 +320,9 @@ static void initialize_vr_config(void)
else
msr.lo |= 0x006f; /* 1.60V */
wrmsr(MSR_VR_MISC_CONFIG2, msr);
/* Set C9/C10 VCC Min */
pcode_mailbox_write(MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE, 0x1f1f);
}
static void configure_pch_power_sharing(void)

3
src/northbridge/intel/haswell/registers/mchbar.h
View File

@ -46,6 +46,9 @@
#define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909
#define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa
#define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb
#define MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE 0x26
#define MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE 0x27
/* Errors are returned back in bits 7:0 */
#define MAILBOX_BIOS_ERROR_NONE 0
#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1