soc/mediatek/mt8195: Add NOR-Flash support

TEST=boot to romstage on MT8195 EVB

Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I450281fb4b1750e59cb76f6b2083f0e2889fd4cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Rex-BC Chen 2021-05-04 10:32:54 +08:00 committed by Hung-Te Lin
parent f46e2caebe
commit 1c92010849
4 changed files with 24 additions and 0 deletions

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@ -17,4 +17,11 @@ config VBOOT
select VBOOT_SEPARATE_VERSTAGE select VBOOT_SEPARATE_VERSTAGE
select VBOOT_RETURN_FROM_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE
config FLASH_DUAL_READ
bool
default y
help
When this option is enabled, the flash controller provides the ability
to dual read mode.
endif endif

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@ -1,6 +1,7 @@
ifeq ($(CONFIG_SOC_MEDIATEK_MT8195),y) ifeq ($(CONFIG_SOC_MEDIATEK_MT8195),y)
bootblock-y += bootblock.c bootblock-y += bootblock.c
bootblock-y += ../common/flash_controller.c
bootblock-y += ../common/gpio.c gpio.c bootblock-y += ../common/gpio.c gpio.c
bootblock-y += ../common/mmu_operations.c bootblock-y += ../common/mmu_operations.c
bootblock-y += ../common/pll.c pll.c bootblock-y += ../common/pll.c pll.c
@ -9,6 +10,7 @@ bootblock-y += ../common/timer.c timer.c
bootblock-y += ../common/uart.c bootblock-y += ../common/uart.c
bootblock-y += ../common/wdt.c bootblock-y += ../common/wdt.c
verstage-y += ../common/flash_controller.c
verstage-y += ../common/gpio.c gpio.c verstage-y += ../common/gpio.c gpio.c
verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
verstage-y += ../common/timer.c timer.c verstage-y += ../common/timer.c timer.c
@ -17,6 +19,7 @@ verstage-y += ../common/wdt.c
romstage-y += ../common/cbmem.c romstage-y += ../common/cbmem.c
romstage-y += emi.c romstage-y += emi.c
romstage-y += ../common/flash_controller.c
romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/gpio.c gpio.c
romstage-y += ../common/pll.c pll.c romstage-y += ../common/pll.c pll.c
romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
@ -30,6 +33,7 @@ romstage-y += ../common/mt6315.c mt6315.c
romstage-y += ../common/mt6359p.c mt6359p.c romstage-y += ../common/mt6359p.c mt6359p.c
ramstage-y += emi.c ramstage-y += emi.c
ramstage-y += ../common/flash_controller.c
ramstage-y += ../common/gpio.c gpio.c ramstage-y += ../common/gpio.c gpio.c
ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
ramstage-y += soc.c ramstage-y += soc.c

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@ -0,0 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _SOC_MEDIATEK_MT8195_SYMBOLS_H_
#define _SOC_MEDIATEK_MT8195_SYMBOLS_H_
#include <symbols.h>
DECLARE_REGION(dram_dma)
#endif /* _SOC_MEDIATEK_MT8195_SYMBOLS_H_ */

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@ -3,6 +3,7 @@
#include <assert.h> #include <assert.h>
#include <device/mmio.h> #include <device/mmio.h>
#include <soc/addressmap.h> #include <soc/addressmap.h>
#include <soc/flash_controller_common.h>
#include <soc/gpio.h> #include <soc/gpio.h>
#include <soc/spi.h> #include <soc/spi.h>
@ -93,6 +94,7 @@ void mtk_spi_set_gpio_pinmux(unsigned int bus, enum spi_pad_mask pad_select)
static const struct spi_ctrlr spi_flash_ctrlr = { static const struct spi_ctrlr spi_flash_ctrlr = {
.max_xfer_size = 65535, .max_xfer_size = 65535,
.flash_probe = mtk_spi_flash_probe,
}; };
const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
@ -103,6 +105,8 @@ const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
}, },
{ {
.ctrlr = &spi_flash_ctrlr, .ctrlr = &spi_flash_ctrlr,
.bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,
.bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,
}, },
}; };