nb/intel/haswell: Add native raminit scaffolding
Implement some scaffolding for Haswell native raminit, like bootmode selection, handling of MRC cache and CPU detection. Change-Id: Icd96649fa045ea7f0f32ae9bfe1e60498d93975b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons
Felix Held
parent
49509189dc
commit
1c9a8d8083
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@ -1,3 +1,4 @@
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## SPDX-License-Identifier: GPL-2.0-or-later
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romstage-y += raminit_main.c
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romstage-y += raminit_native.c
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@ -0,0 +1,104 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <assert.h>
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#include <console/console.h>
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#include <cpu/intel/haswell/haswell.h>
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#include <delay.h>
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#include <device/pci_ops.h>
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#include <northbridge/intel/haswell/chip.h>
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#include <northbridge/intel/haswell/haswell.h>
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#include <northbridge/intel/haswell/raminit.h>
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#include <string.h>
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#include <types.h>
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#include "raminit_native.h"
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struct task_entry {
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enum raminit_status (*task)(struct sysinfo *);
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bool is_enabled;
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const char *name;
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};
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static const struct task_entry cold_boot[] = {
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};
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/* Return a generic stepping value to make stepping checks simpler */
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static enum generic_stepping get_stepping(const uint32_t cpuid)
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{
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switch (cpuid) {
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case CPUID_HASWELL_A0:
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die("Haswell stepping A0 is not supported\n");
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case CPUID_HASWELL_B0:
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case CPUID_HASWELL_ULT_B0:
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case CPUID_CRYSTALWELL_B0:
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return STEPPING_B0;
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case CPUID_HASWELL_C0:
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case CPUID_HASWELL_ULT_C0:
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case CPUID_CRYSTALWELL_C0:
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return STEPPING_C0;
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default:
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/** TODO: Add Broadwell support someday **/
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die("Unknown CPUID 0x%x\n", cpuid);
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}
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}
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static void initialize_ctrl(struct sysinfo *ctrl)
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{
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const struct northbridge_intel_haswell_config *cfg = config_of_soc();
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const enum raminit_boot_mode bootmode = ctrl->bootmode;
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memset(ctrl, 0, sizeof(*ctrl));
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ctrl->cpu = cpu_get_cpuid();
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ctrl->stepping = get_stepping(ctrl->cpu);
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ctrl->dq_pins_interleaved = cfg->dq_pins_interleaved;
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ctrl->bootmode = bootmode;
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}
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static enum raminit_status try_raminit(struct sysinfo *ctrl)
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{
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const struct task_entry *const schedule = cold_boot;
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const size_t length = ARRAY_SIZE(cold_boot);
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enum raminit_status status = RAMINIT_STATUS_UNSPECIFIED_ERROR;
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for (size_t i = 0; i < length; i++) {
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const struct task_entry *const entry = &schedule[i];
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assert(entry);
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assert(entry->name);
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if (!entry->is_enabled)
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continue;
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assert(entry->task);
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printk(RAM_DEBUG, "\nExecuting raminit task %s\n", entry->name);
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status = entry->task(ctrl);
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printk(RAM_DEBUG, "\n");
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if (status) {
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printk(BIOS_ERR, "raminit failed on step %s\n", entry->name);
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break;
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}
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}
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return status;
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}
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void raminit_main(const enum raminit_boot_mode bootmode)
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{
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/*
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* The mighty_ctrl struct. Will happily nuke the pre-RAM stack
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* if left unattended. Make it static and pass pointers to it.
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*/
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static struct sysinfo mighty_ctrl;
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mighty_ctrl.bootmode = bootmode;
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initialize_ctrl(&mighty_ctrl);
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/** TODO: Try more than once **/
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enum raminit_status status = try_raminit(&mighty_ctrl);
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if (status != RAMINIT_STATUS_SUCCESS)
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die("Memory initialization was met with utmost failure and misery\n");
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/** TODO: Implement the required magic **/
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die("NATIVE RAMINIT: More Magic (tm) required.\n");
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}
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@ -1,13 +1,45 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <arch/cpu.h>
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#include <assert.h>
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#include <cbmem.h>
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#include <cf9_reset.h>
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#include <console/console.h>
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#include <cpu/x86/msr.h>
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#include <delay.h>
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#include <device/pci_ops.h>
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#include <mrc_cache.h>
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#include <northbridge/intel/haswell/haswell.h>
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#include <northbridge/intel/haswell/raminit.h>
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#include <southbridge/intel/lynxpoint/me.h>
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#include <southbridge/intel/lynxpoint/pch.h>
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#include <types.h>
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#include "raminit_native.h"
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static void wait_txt_clear(void)
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{
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const struct cpuid_result cpuid = cpuid_ext(1, 0);
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/* Check if TXT is supported */
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if (!(cpuid.ecx & BIT(6)))
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return;
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/* Some TXT public bit */
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if (!(read32p(0xfed30010) & 1))
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return;
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/* Wait for TXT clear */
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do {} while (!(read8p(0xfed40000) & (1 << 7)));
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}
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static enum raminit_boot_mode get_boot_mode(void)
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{
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const uint16_t pmcon_2 = pci_read_config16(PCH_LPC_DEV, GEN_PMCON_2);
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const uint16_t bitmask = GEN_PMCON_2_DISB | GEN_PMCON_2_MEM_SR;
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return (pmcon_2 & bitmask) == bitmask ? BOOTMODE_WARM : BOOTMODE_COLD;
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}
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static bool early_init_native(int s3resume)
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{
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printk(BIOS_DEBUG, "Starting native platform initialisation\n");
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@ -24,6 +56,120 @@ static bool early_init_native(int s3resume)
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return cpu_replaced;
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}
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#define MRC_CACHE_VERSION 1
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struct mrc_data {
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const void *buffer;
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size_t buffer_len;
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};
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static void save_mrc_data(struct mrc_data *md)
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{
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mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, md->buffer, md->buffer_len);
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}
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static struct mrc_data prepare_mrc_cache(void)
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{
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struct mrc_data md = {0};
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md.buffer = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
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MRC_CACHE_VERSION,
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&md.buffer_len);
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return md;
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}
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static const char *const bm_names[] = {
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"BOOTMODE_COLD",
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"BOOTMODE_WARM",
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"BOOTMODE_S3",
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"BOOTMODE_FAST",
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};
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static void clear_disb(void)
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{
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pci_and_config16(PCH_LPC_DEV, GEN_PMCON_2, ~GEN_PMCON_2_DISB);
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}
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static void raminit_reset(void)
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{
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clear_disb();
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system_reset();
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}
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static enum raminit_boot_mode do_actual_raminit(
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struct mrc_data *md,
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const bool s3resume,
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const bool cpu_replaced,
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const enum raminit_boot_mode orig_bootmode)
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{
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enum raminit_boot_mode bootmode = orig_bootmode;
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bool save_data_valid = md->buffer && md->buffer_len == USHRT_MAX; /** TODO: sizeof() **/
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if (s3resume) {
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if (bootmode == BOOTMODE_COLD) {
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printk(BIOS_EMERG, "Memory may not be in self-refresh for S3 resume\n");
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printk(BIOS_EMERG, "S3 resume and cold boot are mutually exclusive\n");
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raminit_reset();
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}
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/* Only a true mad hatter would replace a CPU in S3 */
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if (cpu_replaced) {
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printk(BIOS_EMERG, "Oh no, CPU was replaced during S3\n");
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/*
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* No reason to continue, memory consistency is most likely lost
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* and ME will probably request a reset through DID response too.
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*/
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/** TODO: Figure out why past self commented this out **/
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//raminit_reset();
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}
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bootmode = BOOTMODE_S3;
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if (!save_data_valid) {
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printk(BIOS_EMERG, "No training data, S3 resume is impossible\n");
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/* Failed S3 resume, reset to come up cleanly */
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raminit_reset();
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}
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}
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if (!s3resume && cpu_replaced) {
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printk(BIOS_NOTICE, "CPU was replaced, forcing a cold boot\n");
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/*
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* Looks like the ME will get angry if raminit takes too long.
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* It will report that the CPU has been replaced on next boot.
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* Try to continue anyway. This should not happen in most cases.
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*/
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/** TODO: Figure out why past self commented this out **/
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//save_data_valid = false;
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}
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if (bootmode == BOOTMODE_COLD) {
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/* If possible, promote to a fast boot */
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if (save_data_valid)
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bootmode = BOOTMODE_FAST;
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clear_disb();
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} else if (bootmode == BOOTMODE_WARM) {
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/* If a warm reset happened before raminit is done, force a cold boot */
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if (mchbar_read32(SSKPD) == 0 && mchbar_read32(SSKPD + 4) == 0) {
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printk(BIOS_NOTICE, "Warm reset occurred early in cold boot\n");
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save_data_valid = false;
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}
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if (!save_data_valid)
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bootmode = BOOTMODE_COLD;
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}
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assert(save_data_valid != (bootmode == BOOTMODE_COLD));
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if (save_data_valid) {
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printk(BIOS_INFO, "Using cached memory parameters\n");
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die("RAMINIT: Fast boot is not yet implemented\n");
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}
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printk(RAM_DEBUG, "Initial bootmode: %s\n", bm_names[orig_bootmode]);
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printk(RAM_DEBUG, "Current bootmode: %s\n", bm_names[bootmode]);
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/*
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* And now, the actual memory initialization thing.
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*/
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printk(RAM_DEBUG, "\nStarting native raminit\n");
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raminit_main(bootmode);
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return bootmode;
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}
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void perform_raminit(const int s3resume)
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{
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/*
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@ -32,17 +178,46 @@ void perform_raminit(const int s3resume)
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*/
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const bool cpu_replaced = early_init_native(s3resume);
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(void)cpu_replaced;
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wait_txt_clear();
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wrmsr(0x2e6, (msr_t) {.lo = 0, .hi = 0});
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const enum raminit_boot_mode orig_bootmode = get_boot_mode();
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struct mrc_data md = prepare_mrc_cache();
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const enum raminit_boot_mode bootmode =
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do_actual_raminit(&md, s3resume, cpu_replaced, orig_bootmode);
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/** TODO: report_memory_config **/
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/** TODO: Move after raminit */
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if (intel_early_me_uma_size() > 0) {
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/** TODO: Update status once raminit is implemented **/
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uint8_t me_status = ME_INIT_STATUS_ERROR;
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/*
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* The 'other' success value is to report loss of memory
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* consistency to ME if warm boot was downgraded to cold.
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*/
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uint8_t me_status;
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if (BOOTMODE_WARM == orig_bootmode && BOOTMODE_COLD == bootmode)
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me_status = ME_INIT_STATUS_SUCCESS_OTHER;
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else
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me_status = ME_INIT_STATUS_SUCCESS;
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/** TODO: Remove this once raminit is implemented **/
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me_status = ME_INIT_STATUS_ERROR;
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intel_early_me_init_done(me_status);
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}
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intel_early_me_status();
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/** TODO: Implement the required magic **/
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die("NATIVE RAMINIT: More Magic (tm) required.\n");
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const bool cbmem_was_initted = !cbmem_recovery(s3resume);
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if (s3resume && !cbmem_was_initted) {
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/* Failed S3 resume, reset to come up cleanly */
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printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n");
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system_reset();
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}
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/* Save training data on non-S3 resumes */
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if (!s3resume)
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save_mrc_data(&md);
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/** TODO: setup_sdram_meminfo **/
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}
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@ -0,0 +1,34 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef HASWELL_RAMINIT_NATIVE_H
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#define HASWELL_RAMINIT_NATIVE_H
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enum raminit_boot_mode {
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BOOTMODE_COLD,
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BOOTMODE_WARM,
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BOOTMODE_S3,
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BOOTMODE_FAST,
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};
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enum raminit_status {
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RAMINIT_STATUS_SUCCESS = 0,
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RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
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};
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enum generic_stepping {
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STEPPING_A0 = 1,
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STEPPING_B0 = 2,
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STEPPING_C0 = 3,
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};
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struct sysinfo {
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enum raminit_boot_mode bootmode;
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enum generic_stepping stepping;
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uint32_t cpu; /* CPUID value */
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bool dq_pins_interleaved;
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};
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void raminit_main(enum raminit_boot_mode bootmode);
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#endif
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