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sb/nvidia/mcp55: Drop support 

Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which platforms using this code lack.

Change-Id: I7cd33316140f2cdc83949aa5db7e6f1565982543
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36973
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2019-11-19 17:28:43 +01:00 committed by Kyösti Mälkki
parent 185691eedb
commit 1ca978ee65
27 changed files with 0 additions and 3050 deletions
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45
src/southbridge/nvidia/mcp55/Kconfig
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@ -1,45 +0,0 @@
config SOUTHBRIDGE_NVIDIA_MCP55
bool
select HAVE_USBDEBUG
select IOAPIC
select HAVE_POWER_STATE_AFTER_FAILURE
if SOUTHBRIDGE_NVIDIA_MCP55
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/nvidia/mcp55/bootblock.c"
config EHCI_BAR
hex
default 0xfef00000
config MCP55_USE_NIC
bool
default n
config MCP55_USE_AZA
bool
default n
config MCP55_NUM
int
default 1
config MCP55_PCI_E_X_0
int
default 4
config MCP55_PCI_E_X_1
int
default 4
config MCP55_PCI_E_X_2
int
default 4
config MCP55_PCI_E_X_3
int
default 4
endif

33
src/southbridge/nvidia/mcp55/Makefile.inc
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@ -1,33 +0,0 @@
ifeq ($(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55),y)
ramstage-y += mcp55.c
ramstage-y += azalia.c
ramstage-y += ht.c
ramstage-y += ide.c
ramstage-y += lpc.c
ramstage-y += nic.c
ramstage-y += pci.c
ramstage-y += pcie.c
ramstage-y += sata.c
ramstage-y += smbus.c
ramstage-y += usb2.c
ramstage-y += usb.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
ramstage-y += reset.c
bootblock-y += enable_usbdebug.c
romstage-y += enable_usbdebug.c
ramstage-y += enable_usbdebug.c
romstage-y += early_smbus.c
romstage-y += early_ctrl.c
ifeq ($(CONFIG_MCP55_USE_AZA),y)
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
endif
bootblock-y += romstrap.ld
bootblock-y += romstrap.S
endif

275
src/southbridge/nvidia/mcp55/azalia.c
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@ -1,275 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
* Copyright (C) 2008-2010 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <device/device.h>
#include <device/azalia_device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <device/mmio.h>
#include <delay.h>
#include "mcp55.h"
#if CONFIG(MCP55_USE_AZA)
#define HDA_ICII_REG 0x68
#define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1)
static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
/* Write (val & mask) to port. */
val &= mask;
reg32 = read32(port);
reg32 &= ~mask;
reg32 |= val;
write32(port, reg32);
/* Wait for readback of register to match what was written to it. */
count = 50;
do {
/* Wait 1ms based on BKDG wait time. */
mdelay(1);
reg32 = read32(port);
reg32 &= mask;
} while ((reg32 != val) && --count);
/* Timeout occurred. */
if (!count)
return -1;
return 0;
}
static int codec_detect(u8 *base)
{
u32 reg32;
/* Set bit 0 to 0 to enter reset state (BAR + 0x8)[0]. */
if (set_bits(base + 0x08, 1, 0) == -1)
goto no_codec;
/* Set bit 0 to 1 to exit reset state (BAR + 0x8)[0]. */
if (set_bits(base + 0x08, 1, 1) == -1)
goto no_codec;
/* Read in codec location (BAR + 0xe)[2..0]. */
reg32 = read32(base + 0xe);
reg32 &= 0x0f;
if (!reg32)
goto no_codec;
return reg32;
no_codec:
/* Codec not found. */
/* Put HDA back in reset (BAR + 0x8)[0]. */
set_bits(base + 0x08, 1, 0);
printk(BIOS_DEBUG, "Azalia: No codec!\n");
return 0;
}
static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb)
{
int idx = 0;
while (idx < (cim_verb_data_size / sizeof(u32))) {
u32 verb_size = 4 * cim_verb_data[idx + 2]; /* in u32 */
if (cim_verb_data[idx] != viddid) {
idx += verb_size + 3; /* Skip verb + header. */
continue;
}
*verb = &cim_verb_data[idx + 3];
return verb_size;
}
/* Not all codecs need to load another verb. */
return 0;
}
/**
* Wait 50usec for the codec to indicate it is ready.
* No response would imply that the codec is non-operative.
*/
static int wait_for_ready(u8 *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the same duration. */
int timeout = 50;
while (timeout--) {
u32 reg32 = read32(base + HDA_ICII_REG);
if (!(reg32 & HDA_ICII_BUSY))
return 0;
udelay(1);
}
return -1;
}
/**
* Wait 50usec for the codec to indicate that it accepted the previous command.
* No response would imply that the code is non-operative.
*/
static int wait_for_valid(u8 *base)
{
u32 reg32;
/* Send the verb to the codec. */
reg32 = read32(base + 0x68);
reg32 |= (1 << 0) | (1 << 1);
write32(base + 0x68, reg32);
/* Use a 50 usec timeout - the Linux kernel uses the same duration. */
int timeout = 50;
while (timeout--) {
reg32 = read32(base + HDA_ICII_REG);
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
return 0;
udelay(1);
}
return -1;
}
static void codec_init(struct device *dev, u8 *base, int addr)
{
u32 reg32, verb_size;
const u32 *verb;
int i;
printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr);
/* 1 */
if (wait_for_ready(base) == -1)
return;
reg32 = (addr << 28) | 0x000f0000;
write32(base + 0x60, reg32);
if (wait_for_valid(base) == -1)
return;
reg32 = read32(base + 0x64);
/* 2 */
printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
verb_size = find_verb(dev, reg32, &verb);
if (!verb_size) {
printk(BIOS_DEBUG, "Azalia: No verb!\n");
return;
}
printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size);
/* 3 */
for (i = 0; i < verb_size; i++) {
if (wait_for_ready(base) == -1)
return;
write32(base + 0x60, verb[i]);
if (wait_for_valid(base) == -1)
return;
}
printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
}
static void codecs_init(struct device *dev, u8 *base, u32 codec_mask)
{
int i;
for (i = 2; i >= 0; i--) {
if (codec_mask & (1 << i))
codec_init(dev, base, i);
}
}
#endif
static void azalia_init(struct device *dev)
{
#if CONFIG(MCP55_USE_AZA)
u8 *base;
u32 codec_mask, reg32;
struct resource *res;
u8 reg8;
/* Set bus master. */
reg32 = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
pci_write_config8(dev, 0x3c, 0x0a); // TODO: Unused?
reg8 = pci_read_config8(dev, 0x40);
reg8 |= (1 << 3); /* Clear Clock Detect bit. */
pci_write_config8(dev, 0x40, reg8);
reg8 &= ~(1 << 3); /* Keep CLKDETCLR from clearing the bit over and over. */
pci_write_config8(dev, 0x40, reg8);
reg8 |= (1 << 2); /* Enable clock detection. */
pci_write_config8(dev, 0x40, reg8);
mdelay(1);
reg8 = pci_read_config8(dev, 0x40);
printk(BIOS_DEBUG, "Azalia: codec type: %s\n",
(reg8 & (1 << 1)) ? "Azalia" : "AC97");
reg8 = pci_read_config8(dev, 0x40); /* Audio control */
reg8 |= 1; /* Select Azalia mode. TODO: Control via devicetree.cb. */
pci_write_config8(dev, 0x40, reg8);
reg8 = pci_read_config8(dev, 0x4d); /* Docking status. */
reg8 &= ~(1 << 7); /* Docking not supported. */
pci_write_config8(dev, 0x4d, reg8);
res = find_resource(dev, 0x10);
if (!res)
return;
/*
* NOTE: This will break as soon as the Azalia gets a BAR above
* 4G. Is there anything we can do about it?
*/
base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
codec_mask = codec_detect(base);
if (codec_mask) {
printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
codecs_init(dev, base, codec_mask);
}
#endif
}
static struct pci_operations azalia_pci_ops = {
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations azalia_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = azalia_init,
.scan_bus = 0,
// .enable = mcp55_enable,
.ops_pci = &azalia_pci_ops,
};
static const struct pci_driver azalia __pci_driver = {
.ops = &azalia_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_MCP55_AZA,
};

49
src/southbridge/nvidia/mcp55/bootblock.c
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@ -1,49 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2004 Tyan Computer
* Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
* Copyright (C) 2006,2007 AMD
* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <device/pci_ops.h>
#include "mcp55.h"
static void mcp55_enable_rom(void)
{
u8 byte;
u16 word;
pci_devfn_t addr;
/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
addr = PCI_DEV(0, (MCP55_DEVN_BASE + 1), 0);
/* Set the 15MB enable bits. */
byte = pci_read_config8(addr, 0x88);
byte |= 0xff; /* 256K */
pci_write_config8(addr, 0x88, byte);
byte = pci_read_config8(addr, 0x8c);
byte |= 0xff; /* 1M */
pci_write_config8(addr, 0x8c, byte);
word = pci_read_config16(addr, 0x90);
word |= 0x7fff; /* 15M */
pci_write_config16(addr, 0x90, word);
}
static void bootblock_southbridge_init(void)
{
mcp55_enable_rom();
}

31
src/southbridge/nvidia/mcp55/chip.h
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@ -1,31 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 AMD
* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef SOUTHBRIDGE_NVIDIA_MCP55_CHIP_H
#define SOUTHBRIDGE_NVIDIA_MCP55_CHIP_H
struct southbridge_nvidia_mcp55_config
{
unsigned int ide0_enable : 1;
unsigned int ide1_enable : 1;
unsigned int sata0_enable : 1;
unsigned int sata1_enable : 1;
unsigned int mac_eeprom_smbus;
unsigned int mac_eeprom_addr;
};
#endif

45
src/southbridge/nvidia/mcp55/early_ctrl.c
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@ -1,45 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 AMD
* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <reset.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <southbridge/amd/common/reset.h>
#include "mcp55.h"
void do_soft_reset(void)
{
set_bios_reset();
/* link reset */
outb(0x02, 0x0cf9);
outb(0x06, 0x0cf9);
}
void do_board_reset(void)
{
set_bios_reset();
/* full reset */
outb(0x0a, 0x0cf9);
outb(0x0e, 0x0cf9);
}
void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn)
{
/* The default value for MCP55 is good. */
/* Set VFSMAF (VID/FID System Management Action Field) to 2. */
}

402
src/southbridge/nvidia/mcp55/early_setup_car.c
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@ -1,402 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2006 AMD
* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <delay.h>
#include <console/console.h>
#include <device/pci_ops.h>
#ifdef UNUSED_CODE
int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned int vendorid, unsigned int val);
static int set_ht_link_mcp55(u8 ht_c_num)
{
unsigned int vendorid = 0x10de;
unsigned int val = 0x01610109;
/* NVIDIA MCP55 hardcode, hardware can not set it automatically. */
return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
}
static void setup_ss_table(unsigned int index, unsigned int where, unsigned int control,
const unsigned int *register_values, int max)
{
int i;
unsigned int val;
val = inl(control);
val &= 0xfffffffe;
outl(val, control);
outl(0, index); /* Index */
for (i = 0; i < max; i++) {
unsigned long reg;
reg = register_values[i];
outl(reg, where);
}
val = inl(control);
val |= 1;
outl(val, control);
}
#endif
/* SIZE 0x100 */
#define ANACTRL_IO_BASE 0x2800
#define ANACTRL_REG_POS 0x68
/* SIZE 0x100 */
#define SYSCTRL_IO_BASE 0x2400
#define SYSCTRL_REG_POS 0x64
/* SIZE 0x100 */
#define ACPICTRL_IO_BASE 0x2000
#define ACPICTRL_REG_POS 0x60
/*
* 16 1 1 1 1 8 :0
* 16 0 4 0 0 8 :1
* 16 0 4 2 2 4 :2
* 4 4 4 4 4 8 :3
* 8 8 4 0 0 8 :4
* 8 0 4 4 4 8 :5
*/
#define MCP55_CHIP_REV 3
/* There will be implicit offsets applied, the writes below do not
* really happen at the PCI_ADDR() this expands to.
*/
#define MCP55_DEV(d, f, r) PCI_ADDR(0, d, f, r)
static void mcp55_early_set_port(unsigned int mcp55_num, unsigned int *busn,
unsigned int *devn, unsigned int *io_base)
{
static const unsigned int ctrl_devport_conf[] = {
MCP55_DEV(1, 1, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
MCP55_DEV(1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
MCP55_DEV(1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), ACPICTRL_IO_BASE,
};
int j;
for (j = 0; j < mcp55_num; j++) {
setup_resource_map_offset(ctrl_devport_conf,
ARRAY_SIZE(ctrl_devport_conf),
PCI_DEV(busn[j], devn[j], 0), io_base[j]);
}
}
static void mcp55_early_clear_port(unsigned int mcp55_num, unsigned int *busn,
unsigned int *devn, unsigned int *io_base)
{
static const unsigned int ctrl_devport_conf_clear[] = {
MCP55_DEV(1, 1, ANACTRL_REG_POS), ~(0x0000ff00), 0,
MCP55_DEV(1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
MCP55_DEV(1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), 0,
};
int j;
for (j = 0; j < mcp55_num; j++) {
setup_resource_map_offset(ctrl_devport_conf_clear,
ARRAY_SIZE(ctrl_devport_conf_clear),
PCI_DEV(busn[j], devn[j], 0), io_base[j]);
}
}
static void mcp55_early_pcie_setup(unsigned int busnx, unsigned int devnx,
unsigned int anactrl_io_base, unsigned int pci_e_x)
{
u32 tgio_ctrl, pll_ctrl, dword;
int i;
pci_devfn_t dev;
dev = PCI_DEV(busnx, devnx + 1, 1);
dword = pci_read_config32(dev, 0xe4);
dword |= 0x3f0; /* Disable it at first. */
pci_write_config32(dev, 0xe4, dword);
for (i = 0; i < 3; i++) {
tgio_ctrl = inl(anactrl_io_base + 0xcc);
tgio_ctrl &= ~(3 << 9);
tgio_ctrl |= (i << 9);
outl(tgio_ctrl, anactrl_io_base + 0xcc);
pll_ctrl = inl(anactrl_io_base + 0x30);
pll_ctrl |= (1 << 31);
outl(pll_ctrl, anactrl_io_base + 0x30);
do {
pll_ctrl = inl(anactrl_io_base + 0x30);
} while (!(pll_ctrl & 1));
}
tgio_ctrl = inl(anactrl_io_base + 0xcc);
tgio_ctrl &= ~((7 << 4) | (1 << 8));
tgio_ctrl |= (pci_e_x << 4) | (1 << 8);
outl(tgio_ctrl, anactrl_io_base + 0xcc);
udelay(100); /* Wait 100us. */
dword = pci_read_config32(dev, 0xe4);
dword &= ~(0x3f0); /* Enable. */
pci_write_config32(dev, 0xe4, dword);
mdelay(100); /* Need to wait 100ms. */
}
static void mcp55_early_setup(unsigned int mcp55_num, unsigned int *busn,
unsigned int *devn, unsigned int *io_base,
unsigned int *pci_e_x)
{
static const unsigned int ctrl_conf_1[] = {
RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x10, 0x0007ffff, 0xff78000,
RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xa4, 0xffedffff, 0x0012000,
RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xac, 0xfffffdff, 0x0000200,
RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xb4, 0xfffffffd, 0x0000002,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc0f0f08f, 0x26020230,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x34, 0x00000000, 0x22222222,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, 0x7FFFFFFF, 0x00000000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x2C, 0x7FFFFFFF, 0x80000000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000200,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000400,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, 0xFFFF0FF5, 0x0000F000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, 0xFF00FF00, 0x00100010,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7C, 0xFF0FF0FF, 0x00500500,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0xFFFFFFE7, 0x00000000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFCFFFFF, 0x00300000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x90, 0xFFFF00FF, 0x0000FF00,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x9C, 0xFF00FFFF, 0x00070000,
RES_PCI_IO, MCP55_DEV(0, 0, 0x40), 0x00000000, 0xCB8410DE,
RES_PCI_IO, MCP55_DEV(0, 0, 0x48), 0xFFFFDCED, 0x00002002,
RES_PCI_IO, MCP55_DEV(0, 0, 0x78), 0xFFFFFF8E, 0x00000011,
RES_PCI_IO, MCP55_DEV(0, 0, 0x80), 0xFFFF0000, 0x00009923,
RES_PCI_IO, MCP55_DEV(0, 0, 0x88), 0xFFFFFFFE, 0x00000000,
RES_PCI_IO, MCP55_DEV(0, 0, 0x8C), 0xFFFF0000, 0x0000007F,
RES_PCI_IO, MCP55_DEV(0, 0, 0xDC), 0xFFFEFFFF, 0x00010000,
RES_PCI_IO, MCP55_DEV(1, 0, 0x40), 0x00000000, 0xCB8410DE,
RES_PCI_IO, MCP55_DEV(1, 0, 0x74), 0xFFFFFF7B, 0x00000084,
RES_PCI_IO, MCP55_DEV(1, 0, 0xF8), 0xFFFFFFCF, 0x00000010,
RES_PCI_IO, MCP55_DEV(1, 1, 0xC4), 0xFFFFFFFE, 0x00000001,
RES_PCI_IO, MCP55_DEV(1, 1, 0xF0), 0x7FFFFFFD, 0x00000002,
RES_PCI_IO, MCP55_DEV(1, 1, 0xF8), 0xFFFFFFCF, 0x00000010,
RES_PCI_IO, MCP55_DEV(8, 0, 0x40), 0x00000000, 0xCB8410DE,
RES_PCI_IO, MCP55_DEV(8, 0, 0x68), 0xFFFFFF00, 0x000000FF,
RES_PCI_IO, MCP55_DEV(8, 0, 0xF8), 0xFFFFFFBF, 0x00000040, /* Enable bridge mode. */
RES_PCI_IO, MCP55_DEV(9, 0, 0x40), 0x00000000, 0xCB8410DE,
RES_PCI_IO, MCP55_DEV(9, 0, 0x68), 0xFFFFFF00, 0x000000FF,
RES_PCI_IO, MCP55_DEV(9, 0, 0xF8), 0xFFFFFFBF, 0x00000040, /* Enable bridge mode. */
};
static const unsigned int ctrl_conf_1_1[] = {
RES_PCI_IO, MCP55_DEV(5, 0, 0x40), 0x00000000, 0xCB8410DE,
RES_PCI_IO, MCP55_DEV(5, 0, 0x50), 0xFFFFFFFC, 0x00000003,
RES_PCI_IO, MCP55_DEV(5, 0, 0x64), 0xFFFFFFFE, 0x00000001,
RES_PCI_IO, MCP55_DEV(5, 0, 0x70), 0xFFF0FFFF, 0x00040000,
RES_PCI_IO, MCP55_DEV(5, 0, 0xAC), 0xFFFFF0FF, 0x00000100,
RES_PCI_IO, MCP55_DEV(5, 0, 0x7C), 0xFFFFFFEF, 0x00000000,
RES_PCI_IO, MCP55_DEV(5, 0, 0xC8), 0xFF00FF00, 0x000A000A,
RES_PCI_IO, MCP55_DEV(5, 0, 0xD0), 0xF0FFFFFF, 0x03000000,
RES_PCI_IO, MCP55_DEV(5, 0, 0xE0), 0xF0FFFFFF, 0x03000000,
};
static const unsigned int ctrl_conf_mcp55_only[] = {
RES_PCI_IO, MCP55_DEV(1, 1, 0x40), 0x00000000, 0xCB8410DE,
RES_PCI_IO, MCP55_DEV(1, 1, 0xE0), 0xFFFFFEFF, 0x00000000,
RES_PCI_IO, MCP55_DEV(1, 1, 0xE4), 0xFFFFFFFB, 0x00000000,
RES_PCI_IO, MCP55_DEV(1, 1, 0xE8), 0xFFA9C8FF, 0x00003000,
RES_PCI_IO, MCP55_DEV(4, 0, 0x40), 0x00000000, 0xCB8410DE,
RES_PCI_IO, MCP55_DEV(4, 0, 0xF8), 0xFFFFFFCF, 0x00000010,
RES_PCI_IO, MCP55_DEV(2, 0, 0x40), 0x00000000, 0xCB8410DE,
RES_PCI_IO, MCP55_DEV(2, 1, 0x40), 0x00000000, 0xCB8410DE,
RES_PCI_IO, MCP55_DEV(2, 1, 0x64), 0xF87FFFFF, 0x05000000,
RES_PCI_IO, MCP55_DEV(2, 1, 0x78), 0xFFC07FFF, 0x00360000,
RES_PCI_IO, MCP55_DEV(2, 1, 0x68), 0xFE00D03F, 0x013F2C00,
RES_PCI_IO, MCP55_DEV(2, 1, 0x70), 0xFFF7FFFF, 0x00080000,
RES_PCI_IO, MCP55_DEV(2, 1, 0x7C), 0xFFFFF00F, 0x00000570,
RES_PCI_IO, MCP55_DEV(2, 1, 0xF8), 0xFFFFFFCF, 0x00000010,
RES_PCI_IO, MCP55_DEV(6, 0, 0x04), 0xFFFFFEFB, 0x00000104,
RES_PCI_IO, MCP55_DEV(6, 0, 0x3C), 0xF5FFFFFF, 0x0A000000,
RES_PCI_IO, MCP55_DEV(6, 0, 0x40), 0x00C8FFFF, 0x07330000,
RES_PCI_IO, MCP55_DEV(6, 0, 0x48), 0xFFFFFFF8, 0x00000005,
RES_PCI_IO, MCP55_DEV(6, 0, 0x4C), 0xFE02FFFF, 0x004C0000,
RES_PCI_IO, MCP55_DEV(6, 0, 0x74), 0xFFFFFFC0, 0x00000000,
RES_PCI_IO, MCP55_DEV(6, 0, 0xC0), 0x00000000, 0xCB8410DE,
RES_PCI_IO, MCP55_DEV(6, 0, 0xC4), 0xFFFFFFF8, 0x00000007,
#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10)
/*
* Avoid crash (complete with severe memory corruption!) during initial CAR boot
* in mcp55_early_setup_x() on Fam10h systems by not touching 0x78.
* Interestingly once the system is fully booted into Linux this can be set, but
* not before! Apparently something isn't initialized but the amount of effort
* required to fix this is non-negligible and of unknown real-world benefit
*/
#else
RES_PCI_IO, MCP55_DEV(1, 0, 0x78), 0xC0FFFFFF, 0x19000000,
#endif
#if CONFIG(MCP55_USE_AZA)
RES_PCI_IO, MCP55_DEV(6, 1, 0x40), 0x00000000, 0xCB8410DE,
#endif
#ifdef MCP55_MB_SETUP
/* Play a while with GPIO in MCP55. */
MCP55_MB_SETUP
#endif
#if CONFIG(MCP55_USE_AZA)
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 21, ~(3 << 2), (2 << 2),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 22, ~(3 << 2), (2 << 2),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 46, ~(3 << 2), (2 << 2),
#endif
};
static const unsigned int ctrl_conf_master_only[] = {
RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x80, 0xEFFFFFF, 0x01000000,
/* Master MCP55???? YHLU */
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3 << 2), (0 << 2),
};
static const unsigned int ctrl_conf_2[] = {
/* I didn't put PCI-E related stuff here. */
RES_PCI_IO, MCP55_DEV(0, 0, 0x74), 0xFFFFF00F, 0x000009D0,
RES_PCI_IO, MCP55_DEV(1, 0, 0x74), 0xFFFF7FFF, 0x00008000,
RES_PORT_IO_32, SYSCTRL_IO_BASE + 0x48, 0xFFFEFFFF, 0x00010000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFFFFF00, 0x00000012,
#if CONFIG(MCP55_USE_NIC)
RES_PCI_IO, MCP55_DEV(1, 1, 0xe4), ~((1 << 22) | (1 << 20)), (1 << 22) | (1 << 20),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
#endif
};
int j, i;
for (j = 0; j < mcp55_num; j++) {
mcp55_early_pcie_setup(busn[j], devn[j],
io_base[j] + ANACTRL_IO_BASE, pci_e_x[j]);
setup_resource_map_x_offset(ctrl_conf_1,
ARRAY_SIZE(ctrl_conf_1),
PCI_DEV(busn[j], devn[j], 0), io_base[j]);
for (i = 0; i < 3; i++) { /* Three SATA */
setup_resource_map_x_offset(ctrl_conf_1_1,
ARRAY_SIZE(ctrl_conf_1_1),
PCI_DEV(busn[j], devn[j], i), io_base[j]);
}
if (busn[j] == 0) {
setup_resource_map_x_offset(ctrl_conf_mcp55_only,
ARRAY_SIZE(ctrl_conf_mcp55_only),
PCI_DEV(busn[j], devn[j], 0), io_base[j]);
}
if ((busn[j] == 0) && (mcp55_num>1)) {
setup_resource_map_x_offset(ctrl_conf_master_only,
ARRAY_SIZE(ctrl_conf_master_only),
PCI_DEV(busn[j], devn[j], 0), io_base[j]);
}
setup_resource_map_x_offset(ctrl_conf_2,
ARRAY_SIZE(ctrl_conf_2),
PCI_DEV(busn[j], devn[j], 0), io_base[j]);
}
}
#ifndef HT_CHAIN_NUM_MAX
#define HT_CHAIN_NUM_MAX 4
#define HT_CHAIN_BUSN_D 0x40
#define HT_CHAIN_IOBASE_D 0x4000
#endif
static int mcp55_early_setup_x(void)
{
/* Find out how many MCP55 we have. */
unsigned int busn[HT_CHAIN_NUM_MAX] = {0};
unsigned int devn[HT_CHAIN_NUM_MAX] = {0};
unsigned int io_base[HT_CHAIN_NUM_MAX] = {0};
/*
* FIXME: May have problem if there is different MCP55 HTX card with
* different PCI_E lane allocation. Need to use same trick about
* pci1234 to verify node/link connection.
*/
unsigned int pci_e_x[HT_CHAIN_NUM_MAX] = {
CONFIG_MCP55_PCI_E_X_0, CONFIG_MCP55_PCI_E_X_1,
CONFIG_MCP55_PCI_E_X_2, CONFIG_MCP55_PCI_E_X_3,
};
int mcp55_num = 0, ht_c_index;
unsigned int busnx, devnx;
/* FIXME: Multi PCI segment handling. */
/* Any system that only have IO55 without MCP55? */
for (ht_c_index = 0; ht_c_index < HT_CHAIN_NUM_MAX; ht_c_index++) {
busnx = ht_c_index * HT_CHAIN_BUSN_D;
for (devnx = 0; devnx < 0x20; devnx++) {
u32 id;
pci_devfn_t dev;
dev = PCI_DEV(busnx, devnx, 0);
id = pci_read_config32(dev, PCI_VENDOR_ID);
if (id == 0x036910de) {
busn[mcp55_num] = busnx;
devn[mcp55_num] = devnx;
/* We may have HT chain other than MCP55. */
io_base[mcp55_num]
= ht_c_index * HT_CHAIN_IOBASE_D;
mcp55_num++;
if (mcp55_num == CONFIG_MCP55_NUM)
goto out;
break; /* Only one MCP55 on one chain. */
}
}
}
out:
printk(BIOS_DEBUG, "mcp55_num: %02x\n", mcp55_num);
mcp55_early_set_port(mcp55_num, busn, devn, io_base);
mcp55_early_setup(mcp55_num, busn, devn, io_base, pci_e_x);
mcp55_early_clear_port(mcp55_num, busn, devn, io_base);
return 0;
}

217
src/southbridge/nvidia/mcp55/early_setup_ss.h
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@ -1,217 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2004 Tyan Computer
* Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
static const unsigned int pcie_ss_tbl[] = {
0x0C504103f,
0x0C504103f,
0x0C504103f,
0x0C5042040,
0x0C5042040,
0x0C5042040,
0x0C5043041,
0x0C5043041,
0x0C5043041,
0x0C5043041,
0x0C5044042,
0x0C5044042,
0x0C5044042,
0x0C5045043,
0x0C5045043,
0x0C5045043,
0x0C5045043,
0x0C5045043,
0x0C5046044,
0x0C5046044,
0x0C5046044,
0x0C5046044,
0x0C5047045,
0x0C5047045,
0x0C5047045,
0x0C5047045,
0x0C5047045,
0x0C5048046,
0x0C5048046,
0x0C5048046,
0x0C5048046,
0x0C5049047,
0x0C5049047,
0x0C5049047,
0x0C504a048,
0x0C504a048,
0x0C504b049,
0x0C504b049,
0x0C504a048,
0x0C504a048,
0x0C5049047,
0x0C5049047,
0x0C5048046,
0x0C5048046,
0x0C5048046,
0x0C5047045,
0x0C5047045,
0x0C5047045,
0x0C5047045,
0x0C5047045,
0x0C5046044,
0x0C5046044,
0x0C5046044,
0x0C5046044,
0x0C5045043,
0x0C5045043,
0x0C5045043,
0x0C5044042,
0x0C5044042,
0x0C5044042,
0x0C5043041,
0x0C5043041,
0x0C5042040,
0x0C5042040,
};
static const unsigned int sata_ss_tbl[] = {
0x0c9044042,
0x0c9044042,
0x0c9044042,
0x0c9045043,
0x0c9045043,
0x0c9045043,
0x0c9045043,
0x0c9045043,
0x0c9046044,
0x0c9046044,
0x0c9046044,
0x0c9046044,
0x0c9047045,
0x0c9047045,
0x0c9047045,
0x0c9047045,
0x0c9047045,
0x0c9048046,
0x0c9048046,
0x0c9048046,
0x0c9048046,
0x0c9049047,
0x0c9049047,
0x0c9049047,
0x0c9049047,
0x0c904a048,
0x0c904a048,
0x0c904a048,
0x0c904a048,
0x0c904b049,
0x0c904b049,
0x0c904b049,
0x0c904b049,
0x0c904b049,
0x0c904b049,
0x0c904a048,
0x0c904a048,
0x0c904a048,
0x0c904a048,
0x0c9049047,
0x0c9049047,
0x0c9049047,
0x0c9049047,
0x0c9048046,
0x0c9048046,
0x0c9048046,
0x0c9048046,
0x0c9047045,
0x0c9047045,
0x0c9047045,
0x0c9047045,
0x0c9047045,
0x0c9046044,
0x0c9046044,
0x0c9046044,
0x0c9046044,
0x0c9045043,
0x0c9045043,
0x0c9045043,
0x0c9045043,
0x0c9045043,
0x0c9044042,
0x0c9044042,
0x0c9044042,
};
static const unsigned int cpu_ss_tbl[] = {
0x0C5038036,
0x0C5038036,
0x0C5038036,
0x0C5037035,
0x0C5037035,
0x0C5037035,
0x0C5037035,
0x0C5036034,
0x0C5036034,
0x0C5036034,
0x0C5036034,
0x0C5036034,
0x0C5035033,
0x0C5035033,
0x0C5035033,
0x0C5035033,
0x0C5035033,
0x0C5035033,
0x0C5034032,
0x0C5034032,
0x0C5034032,
0x0C5034032,
0x0C5034032,
0x0C5034032,
0x0C5035033,
0x0C5035033,
0x0C5035033,
0x0C5035033,
0x0C5035033,
0x0C5036034,
0x0C5036034,
0x0C5036034,
0x0C5036034,
0x0C5036034,
0x0C5037035,
0x0C5037035,
0x0C5037035,
0x0C5037035,
0x0C5038036,
0x0C5038036,
0x0C5038036,
0x0C5038036,
0x0C5039037,
0x0C5039037,
0x0C5039037,
0x0C5039037,
0x0C503a038,
0x0C503a038,
0x0C503a038,
0x0C503a038,
0x0C503b039,
0x0C503b039,
0x0C503b039,
0x0C503b039,
0x0C503b039,
0x0C503a038,
0x0C503a038,
0x0C503a038,
0x0C503a038,
0x0C503a038,
0x0C5039037,
0x0C5039037,
0x0C5039037,
0x0C5039037,
};

96
src/southbridge/nvidia/mcp55/early_smbus.c
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@ -1,96 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2004 Tyan Computer
* Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
* Copyright (C) 2006,2007 AMD
* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <device/pci.h>
#include "smbus.h"
#include "mcp55.h"
#define SMBUS0_IO_BASE 0x1000
#define SMBUS1_IO_BASE (0x1000 + (1 << 8))
/* Size: 0x40 */
void enable_smbus(void)
{
pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x10de, 0x0368), 0);
if (dev == PCI_DEV_INVALID)
die("SMBus controller not found\n");
/* Set SMBus I/O base. */
pci_write_config32(dev, 0x20, SMBUS0_IO_BASE | 1);
pci_write_config32(dev, 0x24, SMBUS1_IO_BASE | 1);
/* Set SMBus I/O space enable. */
pci_write_config16(dev, 0x4, 0x01);
/* Clear any lingering errors, so the transaction will run. */
outb(inb(SMBUS0_IO_BASE + SMBHSTSTAT), SMBUS0_IO_BASE + SMBHSTSTAT);
outb(inb(SMBUS1_IO_BASE + SMBHSTSTAT), SMBUS1_IO_BASE + SMBHSTSTAT);
}
int smbus_recv_byte(unsigned int device)
{
return do_smbus_recv_byte(SMBUS0_IO_BASE, device);
}
int smbus_send_byte(unsigned int device, unsigned char val)
{
return do_smbus_send_byte(SMBUS0_IO_BASE, device, val);
}
int smbus_read_byte(unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS0_IO_BASE, device, address);
}
int smbus_write_byte(unsigned int device, unsigned int address,
unsigned char val)
{
return do_smbus_write_byte(SMBUS0_IO_BASE, device, address, val);
}
int smbusx_recv_byte(unsigned int smb_index, unsigned int device)
{
return do_smbus_recv_byte(SMBUS0_IO_BASE + (smb_index << 8), device);
}
int smbusx_send_byte(unsigned int smb_index, unsigned int device,
unsigned char val)
{
return do_smbus_send_byte(SMBUS0_IO_BASE + (smb_index << 8),
device, val);
}
int smbusx_read_byte(unsigned int smb_index, unsigned int device,
unsigned int address)
{
return do_smbus_read_byte(SMBUS0_IO_BASE + (smb_index << 8),
device, address);
}
int smbusx_write_byte(unsigned int smb_index, unsigned int device,
unsigned int address, unsigned char val)
{
return do_smbus_write_byte(SMBUS0_IO_BASE + (smb_index << 8),
device, address, val);
}

43
src/southbridge/nvidia/mcp55/enable_usbdebug.c
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@ -1,43 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2004 Tyan Computer
* Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
* Copyright (C) 2006,2007 AMD
* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
// Use simple device model for this file even in ramstage
#define __SIMPLE_DEVICE__
#include <stdint.h>
#include <device/pci_ops.h>
#include <device/pci_ehci.h>
#include <device/pci_def.h>
#include "mcp55.h"
pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
{
return PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */
}
void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
{
u32 dword;
/* Write the port number to 0x74[15:12]. */
dword = pci_read_config32(dev, 0x74);
dword &= ~(0xf << 12);
dword |= (port << 12);
pci_write_config32(dev, 0x74, dword);
}

169
src/southbridge/nvidia/mcp55/fadt.c
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@ -1,169 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2004 Nick Barker <nick.barker9@btinternet.com>
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
* Copyright (C) 2009 Harald Gutmann <harald.gutmann@gmx.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
#include <device/device.h>
#include <device/pci_ids.h>
#include <version.h>
extern unsigned int pm_base;
/* Create the Fixed ACPI Description Tables (FADT) for this board. */
void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
{
acpi_header_t *header = &(fadt->header);
struct device *dev;
int is_mcp55 = 0;
dev = dev_find_device(PCI_VENDOR_ID_NVIDIA,
PCI_DEVICE_ID_NVIDIA_MCP55_LPC, 0);
if (dev)
is_mcp55 = 1;
memset((void *) fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4);
header->length = sizeof(acpi_fadt_t);
header->revision = ACPI_FADT_REV_ACPI_1_0;
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
memcpy(header->asl_compiler_id, ASLC, 4);
header->asl_compiler_revision = asl_revision;
printk(BIOS_INFO, "ACPI: pm_base: %u...\n", pm_base);
fadt->firmware_ctrl = (u32)facs;
fadt->dsdt = (u32)dsdt;
fadt->preferred_pm_profile = 1; //check
fadt->sci_int = 9;
/* disable system management mode by setting to 0 */
fadt->smi_cmd = 0x0; //pm_base+0x42e; (value from proprietary acpi fadt)
fadt->acpi_enable = 0xa1;
fadt->acpi_disable = 0xa0;
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = 0x0;
fadt->pm1a_evt_blk = pm_base;
fadt->pm1b_evt_blk = 0x0;
fadt->pm1a_cnt_blk = pm_base + 0x4;
fadt->pm1b_cnt_blk = 0x0;
fadt->pm2_cnt_blk = pm_base + 0x1c;
fadt->pm_tmr_blk = pm_base + 0x8;
fadt->gpe0_blk = pm_base + 0x20;
fadt->pm1_evt_len = 4;
fadt->pm1_cnt_len = 2;
fadt->pm2_cnt_len = 1;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 8;
if (is_mcp55) {
fadt->gpe1_blk = pm_base + 0x4a0;
fadt->gpe1_base = 0x20;
fadt->gpe1_blk_len = 0x10;
}
else {
fadt->gpe1_blk = 0x0;
fadt->gpe1_base = 0x0;
fadt->gpe1_blk_len = 0x0;
}
fadt->cst_cnt = 0;
fadt->p_lvl2_lat = 0x65;
fadt->p_lvl3_lat = 0x3e9;
fadt->flush_size = 0;
fadt->flush_stride = 0;
fadt->duty_offset = 1;
fadt->duty_width = 3;
fadt->day_alrm = 0x7d;
fadt->mon_alrm = 0x7e;
fadt->century = 0x32;
fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE;
fadt->flags = 0x4a5;
fadt->reset_reg.space_id = 0;
fadt->reset_reg.bit_width = 0;
fadt->reset_reg.bit_offset = 0;
fadt->reset_reg.access_size = 0;
fadt->reset_reg.addrl = 0x0;
fadt->reset_reg.addrh = 0x0;
fadt->reset_value = 0;
fadt->x_firmware_ctl_l = (u32)facs;
fadt->x_firmware_ctl_h = 0;
fadt->x_dsdt_l = (u32)dsdt;
fadt->x_dsdt_h = 0;
fadt->x_pm1a_evt_blk.space_id = 1;
fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
fadt->x_pm1a_evt_blk.bit_offset = 0;
fadt->x_pm1a_evt_blk.access_size = 0;
fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
fadt->x_pm1a_evt_blk.addrh = 0x0;
fadt->x_pm1b_evt_blk.space_id = 1;
fadt->x_pm1b_evt_blk.bit_width = fadt->pm1_evt_len * 8;
fadt->x_pm1b_evt_blk.bit_offset = 0;
fadt->x_pm1b_evt_blk.access_size = 0;
fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk;
fadt->x_pm1b_evt_blk.addrh = 0x0;
fadt->x_pm1a_cnt_blk.space_id = 1;
fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
fadt->x_pm1a_cnt_blk.bit_offset = 0;
fadt->x_pm1a_cnt_blk.access_size = 0;
fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
fadt->x_pm1a_cnt_blk.addrh = 0x0;
fadt->x_pm1b_cnt_blk.space_id = 1;
fadt->x_pm1b_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
fadt->x_pm1b_cnt_blk.bit_offset = 0;
fadt->x_pm1b_cnt_blk.access_size = 0;
fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk;
fadt->x_pm1b_cnt_blk.addrh = 0x0;
fadt->x_pm2_cnt_blk.space_id = 1;
fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
fadt->x_pm2_cnt_blk.bit_offset = 0;
fadt->x_pm2_cnt_blk.access_size = 0;
fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
fadt->x_pm2_cnt_blk.addrh = 0x0;
fadt->x_pm_tmr_blk.space_id = 1;
fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.access_size = 0;
fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.space_id = 1;
fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.access_size = 0;
fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
fadt->x_gpe0_blk.addrh = 0x0;
fadt->x_gpe1_blk.space_id = 1;
fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;
fadt->x_gpe1_blk.bit_offset = 0;
fadt->x_gpe1_blk.access_size = 0;
fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;
fadt->x_gpe1_blk.addrh = 0x0;
header->checksum = acpi_checksum((void *) fadt, header->length);
}

47
src/southbridge/nvidia/mcp55/ht.c
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@ -1,47 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2004 Tyan Computer
* Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
* Copyright (C) 2006,2007 AMD
* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <arch/acpi.h>
#include "mcp55.h"
#if CONFIG(HAVE_ACPI_TABLES)
unsigned long acpi_fill_mcfg(unsigned long current)
{
/* Not implemented */
return current;
}
#endif
static struct device_operations ht_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = 0,
.scan_bus = 0,
.ops_pci = &mcp55_pci_ops,
};
static const struct pci_driver ht_driver __pci_driver = {
.ops = &ht_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_MCP55_HT,
};

78
src/southbridge/nvidia/mcp55/ide.c
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@ -1,78 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2004 Tyan Computer
* Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
* Copyright (C) 2006,2007 AMD
* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "chip.h"
#include "mcp55.h"
static void ide_init(struct device *dev)
{
struct southbridge_nvidia_mcp55_config *conf;
u32 dword;
u16 word;
u8 byte;
conf = dev->chip_info;
word = pci_read_config16(dev, 0x50);
/* Ensure prefetch is disabled. */
word &= ~((1 << 15) | (1 << 13));
if (conf->ide1_enable) {
/* Enable secondary IDE interface. */
word |= (1 << 0);
printk(BIOS_DEBUG, "IDE1\t");
}
if (conf->ide0_enable) {
/* Enable primary IDE interface. */
word |= (1 << 1);
printk(BIOS_DEBUG, "IDE0\n");
}
word |= (1 << 12);
word |= (1 << 14);
pci_write_config16(dev, 0x50, word);
byte = 0x20; /* Latency: 64-->32 */
pci_write_config8(dev, 0xd, byte);
dword = pci_read_config32(dev, 0xf8);
dword |= 12;
pci_write_config32(dev, 0xf8, dword);
}
static struct device_operations ide_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = ide_init,
.scan_bus = 0,
// .enable = mcp55_enable,
.ops_pci = &mcp55_pci_ops,
};
static const struct pci_driver ide_driver __pci_driver = {
.ops = &ide_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_MCP55_IDE,
};

284
src/southbridge/nvidia/mcp55/lpc.c
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@ -1,284 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2003 Linux Networx
* Copyright (C) 2003 SuSE Linux AG
* Copyright (C) 2004 Tyan Computer
* Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
* Copyright (C) 2006,2007 AMD
* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pnp.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <arch/io.h>
#include <arch/ioapic.h>
#include <cpu/x86/lapic.h>
#include <arch/acpi.h>
#include <stdlib.h>
#include <cpu/amd/powernow.h>
#include "mcp55.h"
#define NMI_OFF 0
// 0x7a or e3
#define PREVIOUS_POWER_STATE 0x7A
#define MAINBOARD_POWER_OFF 0
#define MAINBOARD_POWER_ON 1
#define SLOW_CPU_OFF 0
#define SLOW_CPU__ON 1
static void lpc_common_init(struct device *dev, int master)
{
u8 byte;
void *ioapic_base;
/* IOAPIC initialization. */
byte = pci_read_config8(dev, 0x74);
byte |= (1 << 0); /* Enable IOAPIC. */
pci_write_config8(dev, 0x74, byte);
ioapic_base = (void *)pci_read_config32(dev, PCI_BASE_ADDRESS_1); /* 0x14 */
if (master)
setup_ioapic(ioapic_base, 0);
else
clear_ioapic(ioapic_base);
}
static void lpc_slave_init(struct device *dev)
{
lpc_common_init(dev, 0);
}
static void enable_hpet(struct device *dev)
{
unsigned long hpet_address;
pci_write_config32(dev, 0x44, CONFIG_HPET_ADDRESS|1);
hpet_address=pci_read_config32(dev, 0x44) & 0xfffffffe;
printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address);
}
static void lpc_init(struct device *dev)
{
u8 byte, byte_old;
int on, nmi_option;
lpc_common_init(dev, 1);
/* power after power fail */
#if 1
on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
get_option(&on, "power_on_after_fail");
byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
byte &= ~0x40;
if (!on)
byte |= 0x40;
pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off");
#endif
/* Throttle the CPU speed down for testing. */
on = SLOW_CPU_OFF;
get_option(&on, "slow_cpu");
if (on) {
u16 pm10_bar;
pm10_bar = (pci_read_config16(dev, 0x60) & 0xff00);
outl(((on << 1) + 0x10), (pm10_bar + 0x10));
inl(pm10_bar + 0x10);
on = 8 - on;
printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n",
(on * 12) + (on >> 1), (on & 1) * 5);
}
/* Enable error reporting. */
/* Set up sync flood detected. */
byte = pci_read_config8(dev, 0x47);
byte |= (1 << 1);
pci_write_config8(dev, 0x47, byte);
/* Set up NMI on errors. */
byte = inb(0x70); /* RTC70 */
byte_old = byte;
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
if (nmi_option)
byte &= ~(1 << 7); /* Set NMI. */
else
byte |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */
if (byte != byte_old)
outb(byte, 0x70);
/* Initialize the real time clock. */
cmos_init(0);
/* Initialize ISA DMA. */
isa_dma_init();
/* Initialize the High Precision Event Timers (HPET). */
enable_hpet(dev);
}
static void mcp55_lpc_read_resources(struct device *dev)
{
struct resource *res;
/* Get the normal PCI resources of this device. */
/* We got one for APIC, or one more for TRAP. */
pci_dev_read_resources(dev);
/* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->base = 0;
res->size = 0x1000;
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
res->base = 0xff800000;
res->size = 0x00800000; /* 8 MB for flash */
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
/**
* Enable resources for children devices.
*
* @param dev The device whose children's resources are to be enabled.
*/
static void mcp55_lpc_enable_childrens_resources(struct device *dev)
{
u32 reg, reg_var[4];
int i, var_num = 0;
struct bus *link;
reg = pci_read_config32(dev, 0xa0);
for (link = dev->link_list; link; link = link->next) {
struct device *child;
for (child = link->children; child; child = child->sibling) {
if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
struct resource *res;
for (res = child->resource_list; res; res = res->next) {
unsigned long base, end; /* Don't need long long. */
if (!(res->flags & IORESOURCE_IO))
continue;
base = res->base;
end = resource_end(res);
printk(BIOS_DEBUG, "mcp55 lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
switch (base) {
case 0x3f8: /* COM1 */
reg |= (1 << 0);
break;
case 0x2f8: /* COM2 */
reg |= (1 << 1);
break;
case 0x378: /* Parallel 1 */
reg |= (1 << 24);
break;
case 0x3f0: /* FD0 */
reg |= (1 << 20);
break;
case 0x220: /* Audio 0 */
reg |= (1 << 8);
break;
case 0x300: /* Midi 0 */
reg |= (1 << 12);
break;
}
if ((base == 0x290)
|| (base >= 0x400)) {
/* Only 4 var; compact them? */
if (var_num >= 4)
continue;
reg |= (1 << (28 + var_num));
reg_var[var_num++] = (base & 0xffff) | ((end & 0xffff) << 16);
}
}
}
}
}
pci_write_config32(dev, 0xa0, reg);
for (i = 0; i < var_num; i++)
pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]);
}
static void mcp55_lpc_enable_resources(struct device *dev)
{
pci_dev_enable_resources(dev);
mcp55_lpc_enable_childrens_resources(dev);
}
#if CONFIG(HAVE_ACPI_TABLES)
static void southbridge_acpi_fill_ssdt_generator(struct device *device)
{
amd_generate_powernow(0, 0, 0);
}
#endif
static struct device_operations lpc_ops = {
.read_resources = mcp55_lpc_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = mcp55_lpc_enable_resources,
#if CONFIG(HAVE_ACPI_TABLES)
.acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator,
.write_acpi_tables = acpi_write_hpet,
#endif
.init = lpc_init,
.scan_bus = scan_static_bus,
.ops_pci = &mcp55_pci_ops,
};
static const unsigned short lpc_ids[] = {
PCI_DEVICE_ID_NVIDIA_MCP55_LPC,
PCI_DEVICE_ID_NVIDIA_MCP55_PRO,
PCI_DEVICE_ID_NVIDIA_MCP55_LPC_2,
PCI_DEVICE_ID_NVIDIA_MCP55_LPC_3,
PCI_DEVICE_ID_NVIDIA_MCP55_LPC_4,
PCI_DEVICE_ID_NVIDIA_MCP55_LPC_5,
PCI_DEVICE_ID_NVIDIA_MCP55_LPC_6,
0
};
static const struct pci_driver lpc_driver __pci_driver = {
.ops = &lpc_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.devices = lpc_ids,
};
static struct device_operations lpc_slave_ops = {
.read_resources = mcp55_lpc_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
#if CONFIG(HAVE_ACPI_TABLES)
.write_acpi_tables = acpi_write_hpet,
#endif
.init = lpc_slave_init,
.ops_pci = &mcp55_pci_ops,
};
static const struct pci_driver lpc_driver_slave __pci_driver = {
.ops = &lpc_slave_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_MCP55_SLAVE,
};

234
src/southbridge/nvidia/mcp55/mcp55.c
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@ -1,234 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2004 Tyan Computer
* Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
* Copyright (C) 2006,2007 AMD
* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "mcp55.h"
static u32 final_reg;
static struct device *find_lpc_dev(struct device *dev, unsigned int devfn)
{
struct device *lpc_dev;
lpc_dev = pcidev_path_behind(dev->bus, devfn);
if (!lpc_dev)
return lpc_dev;
if ((lpc_dev->vendor != PCI_VENDOR_ID_NVIDIA) || (
(lpc_dev->device < PCI_DEVICE_ID_NVIDIA_MCP55_LPC) ||
(lpc_dev->device > PCI_DEVICE_ID_NVIDIA_MCP55_PRO)))
{
u32 id;
id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
if ((id < (PCI_VENDOR_ID_NVIDIA
| (PCI_DEVICE_ID_NVIDIA_MCP55_LPC << 16))) ||
(id > (PCI_VENDOR_ID_NVIDIA
| (PCI_DEVICE_ID_NVIDIA_MCP55_PRO << 16))))
{
lpc_dev = 0;
}
}
return lpc_dev;
}
void mcp55_enable(struct device *dev)
{
struct device *lpc_dev = NULL, *sm_dev = NULL;
unsigned int index = 0, index2 = 0;
u32 reg_old, reg;
u8 byte;
unsigned int deviceid, vendorid, devfn;
int i;
if (dev->device == 0x0000) {
vendorid = pci_read_config32(dev, PCI_VENDOR_ID);
deviceid = (vendorid >> 16) & 0xffff;
} else {
deviceid = dev->device;
}
devfn = (dev->path.pci.devfn) & ~7;
switch (deviceid) {
case PCI_DEVICE_ID_NVIDIA_MCP55_HT:
return;
case PCI_DEVICE_ID_NVIDIA_MCP55_SM2: //?
index = 16;
break;
case PCI_DEVICE_ID_NVIDIA_MCP55_USB:
devfn -= (1 << 3);
index = 8;
break;
case PCI_DEVICE_ID_NVIDIA_MCP55_USB2:
devfn -= (1 << 3);
index = 20;
break;
case PCI_DEVICE_ID_NVIDIA_MCP55_NIC: // two
case PCI_DEVICE_ID_NVIDIA_MCP55_NIC_BRIDGE: // two
devfn -= (7 << 3);
index = 10;
for (i = 0; i < 2; i++) {
lpc_dev = find_lpc_dev(dev, devfn - (i << 3));
if (!lpc_dev)
continue;
index -= i;
devfn -= (i << 3);
break;
}
break;
case PCI_DEVICE_ID_NVIDIA_MCP55_AZA:
devfn -= (5 << 3);
index = 11;
break;
case PCI_DEVICE_ID_NVIDIA_MCP55_IDE:
devfn -= (3 << 3);
index = 14;
break;
case PCI_DEVICE_ID_NVIDIA_MCP55_SATA0: // three
case PCI_DEVICE_ID_NVIDIA_MCP55_SATA1: // three
devfn -= (4 << 3);
index = 22;
i = (dev->path.pci.devfn) & 7;
if (i > 0)
index -= (i + 3);
break;
case PCI_DEVICE_ID_NVIDIA_MCP55_PCI:
devfn -= (5 << 3);
index = 15;
break;
case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_A:
devfn -= (0x9 << 3); // to LPC
index2 = 9;
break;
case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_B_C: // two
devfn -= (0xa << 3); // to LPC
index2 = 8;
for (i = 0; i < 2; i++) {
lpc_dev = find_lpc_dev(dev, devfn - (i << 3));
if (!lpc_dev)
continue;
index2 -= i;
devfn -= (i << 3);
break;
}
break;
case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D:
devfn -= (0xc << 3); // to LPC
index2 = 6;
break;
case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_E:
devfn -= (0xd << 3); // to LPC
index2 = 5;
break;
case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_F:
devfn -= (0xe << 3); // to LPC
index2 = 4;
break;
default:
index = 0;
}
if (!lpc_dev)
lpc_dev = find_lpc_dev(dev, devfn);
if (!lpc_dev)
return;
if (index2 != 0) {
sm_dev = pcidev_path_behind(dev->bus, devfn + 1);
if (!sm_dev)
return;
if (sm_dev) {
reg_old = reg = pci_read_config32(sm_dev, 0xe4);
if (!dev->enabled)
reg |= (1<<index2); /* Disable it. */
if (reg != reg_old)
pci_write_config32(sm_dev, 0xe4, reg);
}
index2 = 0;
return;
}
if (index == 0) { // for LPC
/* Expose IOAPIC base. */
byte = pci_read_config8(lpc_dev, 0x74);
byte |= (1 << 1); /* Expose the BAR. */
pci_write_config8(dev, 0x74, byte);
/* Expose trap base. */
byte = pci_read_config8(lpc_dev, 0xdd);
byte |= (1 << 0) | (1 << 3); /* Expose BAR and enable write. */
pci_write_config8(dev, 0xdd, byte);
return;
}
if (index == 16) {
sm_dev = pcidev_path_behind(dev->bus, devfn + 1);
if (!sm_dev)
return;
final_reg = pci_read_config32(sm_dev, 0xe8);
final_reg &= ~((1 << 16) | (1 << 8) | (1 << 20) | (1 << 14)
| (1 << 22) | (1 << 18) | (1 << 17) | (1 << 15)
| (1 << 11) | (1 << 10) | (1 << 9));
pci_write_config32(sm_dev, 0xe8, final_reg); /* Enable all at first. */
}
if (!dev->enabled) {
final_reg |= (1 << index); /* Disable it. */
/*
* The reason for using final_reg is that if func 1 is disabled,
* then func 2 will become func 1.
* Because of this, we need loop through disabling them all at
* the same time.
*/
}
/* NIC1 is the final, we need update final reg to 0xe8. */
if (index == 9) {
sm_dev = pcidev_path_behind(dev->bus, devfn + 1);
if (!sm_dev)
return;
reg_old = pci_read_config32(sm_dev, 0xe8);
if (final_reg != reg_old)
pci_write_config32(sm_dev, 0xe8, final_reg);
}
}
static void mcp55_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
pci_write_config32(dev, 0x40,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
struct pci_operations mcp55_pci_ops = {
.set_subsystem = mcp55_set_subsystem,
};
struct chip_operations southbridge_nvidia_mcp55_ops = {
CHIP_NAME("NVIDIA MCP55 Southbridge")
.enable_dev = mcp55_enable,
};

49
src/southbridge/nvidia/mcp55/mcp55.h
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@ -1,49 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 AMD
* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef SOUTHBRIDGE_NVIDIA_MCP55_MCP55_H
#define SOUTHBRIDGE_NVIDIA_MCP55_MCP55_H
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
#else
#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
#endif
#ifndef __ROMCC__
#include <device/device.h>
void mcp55_enable(struct device *dev);
extern struct pci_operations mcp55_pci_ops;
#endif
void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn);
void enable_smbus(void);
/* Concflict declarations with <device/smbus.h>. */
#if !ENV_RAMSTAGE
int smbus_recv_byte(unsigned int device);
int smbus_send_byte(unsigned int device, unsigned char val);
int smbus_read_byte(unsigned int device, unsigned int address);
int smbus_write_byte(unsigned int device, unsigned int address, unsigned char val);
int smbusx_recv_byte(unsigned int smb_index, unsigned int device);
int smbusx_send_byte(unsigned int smb_index, unsigned int device, unsigned char val);
int smbusx_read_byte(unsigned int smb_index, unsigned int device, unsigned int address);
int smbusx_write_byte(unsigned int smb_index, unsigned int device, unsigned int address,
unsigned char val);
#endif /* !ENV_RAMSTAGE */
#endif

201
src/southbridge/nvidia/mcp55/nic.c
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@ -1,201 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2004 Tyan Computer
* Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
* Copyright (C) 2006,2007 AMD
* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <device/device.h>
#include <device/smbus.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <device/mmio.h>
#include <delay.h>
#include "chip.h"
#include "mcp55.h"
static int phy_read(u8 *base, unsigned int phy_addr, unsigned int phy_reg)
{
u32 dword;
unsigned int loop = 0x100;
write32(base + 0x190, 0x8000); /* Clear MDIO lock bit. */
mdelay(1);
dword = read32(base + 0x190);
if (dword & (1 << 15))
return -1;
write32(base + 0x180, 1);
write32(base + 0x190, (phy_addr << 5) | (phy_reg));
do {
dword = read32(base + 0x190);
if (--loop == 0)
return -4;
} while ((dword & (1 << 15)));
dword = read32(base + 0x180);
if (dword & 1)
return -3;
dword = read32(base + 0x194);
return dword;
}
static void phy_detect(u8 *base)
{
u32 dword;
int i, val;
unsigned int id;
dword = read32(base + 0x188);
dword &= ~(1 << 20);
write32(base + 0x188, dword);
phy_read(base, 0, 1);
for (i = 1; i <= 32; i++) {
int phyaddr = i & 0x1f;
val = phy_read(base, phyaddr, 1);
if (val < 0)
continue;
if ((val & 0xffff) == 0xffff)
continue;
if ((val & 0xffff) == 0)
continue;
if (!(val & 1))
break; /* Ethernet PHY */
val = phy_read(base, phyaddr, 3);
if (val < 0 || val == 0xffff)
continue;
id = val & 0xfc00;
val = phy_read(base, phyaddr, 2);
if (val < 0 || val == 0xffff)
continue;
id |= ((val & 0xffff) << 16);
printk(BIOS_DEBUG, "MCP55 MAC PHY ID 0x%08x PHY ADDR %d\n",
id, i);
// if ((id == 0xe0180000) || (id == 0x0032cc00))
break;
}
if (i > 32)
printk(BIOS_DEBUG, "MCP55 MAC PHY not found\n");
}
static void nic_init(struct device *dev)
{
u8 *base;
u32 mac_h = 0, mac_l = 0;
int eeprom_valid = 0;
struct southbridge_nvidia_mcp55_config *conf;
static u32 nic_index = 0;
struct resource *res;
res = find_resource(dev, 0x10);
if (!res)
return;
base = res2mmio(res, 0, 0);
phy_detect(base);
#define NvRegPhyInterface 0xC0
#define PHY_RGMII 0x10000000
write32(base + NvRegPhyInterface, PHY_RGMII);
conf = dev->chip_info;
if (conf->mac_eeprom_smbus != 0) {
// read MAC address from EEPROM at first
struct device *dev_eeprom;
dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr);
if (dev_eeprom) {
// if that is valid we will use that
unsigned char dat[6];
int status;
int i;
for (i=0;i<6;i++) {
status = smbus_read_byte(dev_eeprom, i);
if (status < 0) break;
dat[i] = status & 0xff;
}
if (status >= 0) {
mac_l = 0;
for (i=3;i>=0;i--) {
mac_l <<= 8;
mac_l += dat[i];
}
if (mac_l != 0xffffffff) {
mac_l += nic_index;
mac_h = 0;
for (i=5;i>=4;i--) {
mac_h <<= 8;
mac_h += dat[i];
}
eeprom_valid = 1;
}
}
}
}
// if that is invalid we will read that from romstrap
if (!eeprom_valid) {
u32 *mac_pos;
mac_pos = (u32 *)0xffffffd0; // refer to romstrap.inc and romstrap.ld
mac_l = read32(mac_pos) + nic_index; // overflow?
mac_h = read32(mac_pos + 1);
}
#if 1
// set that into NIC MMIO
#define NvRegMacAddrA 0xA8
#define NvRegMacAddrB 0xAC
write32(base + NvRegMacAddrA, mac_l);
write32(base + NvRegMacAddrB, mac_h);
#else
// set that into NIC
pci_write_config32(dev, 0xa8, mac_l);
pci_write_config32(dev, 0xac, mac_h);
#endif
nic_index++;
}
static struct device_operations nic_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = nic_init,
.scan_bus = 0,
// .enable = mcp55_enable,
.ops_pci = &mcp55_pci_ops,
};
static const struct pci_driver nic_driver __pci_driver = {
.ops = &nic_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_MCP55_NIC,
};
static const struct pci_driver nic_bridge_driver __pci_driver = {
.ops = &nic_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_MCP55_NIC_BRIDGE,
};

97
src/southbridge/nvidia/mcp55/pci.c
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@ -1,97 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2004 Tyan Computer
* Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
* Copyright (C) 2006,2007 AMD
* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <device/device.h>
#include <device/resource.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "mcp55.h"
static void pci_init(struct device *dev)
{
u32 dword;
u16 word;
struct device *pci_domain_dev;
struct resource *mem, *pref;
/* System error enable */
dword = pci_read_config32(dev, 0x04);
dword |= (1<<8); /* System error enable */
dword |= (1<<30); /* Clear possible errors */
pci_write_config32(dev, 0x04, dword);
#if 1
//only need (a01,xx]
word = pci_read_config16(dev, 0x48);
word |= (1<<0); /* MRL2MRM */
word |= (1<<2); /* MR2MRM */
pci_write_config16(dev, 0x48, word);
#endif
#if 1
dword = pci_read_config32(dev, 0x4c);
dword |= 0x00440000; /*TABORT_SER_ENABLE Park Last Enable.*/
pci_write_config32(dev, 0x4c, dword);
#endif
pci_domain_dev = dev->bus->dev;
while (pci_domain_dev) {
if (pci_domain_dev->path.type == DEVICE_PATH_DOMAIN)
break;
pci_domain_dev = pci_domain_dev->bus->dev;
}
if (!pci_domain_dev)
return; /* Impossible */
pref = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(2,0));
mem = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(1,0));
if (!mem)
return; /* Impossible */
if (!pref || pref->base > mem->base) {
dword = mem->base & (0xffff0000UL);
printk(BIOS_DEBUG, "PCI DOMAIN mem base = 0x%010Lx\n", mem->base);
} else {
dword = pref->base & (0xffff0000UL);
printk(BIOS_DEBUG, "PCI DOMAIN pref base = 0x%010Lx\n", pref->base);
}
printk(BIOS_DEBUG, "[0x50] <-- 0x%08x\n", dword);
pci_write_config32(dev, 0x50, dword); /* TOM */
}
static struct device_operations pci_ops = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources,
.init = pci_init,
.scan_bus = pci_scan_bridge,
// .enable = mcp55_enable,
.reset_bus = pci_bus_reset,
};
static const struct pci_driver pci_driver __pci_driver = {
.ops = &pci_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_MCP55_PCI,
};

61
src/southbridge/nvidia/mcp55/pcie.c
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@ -1,61 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2004 Tyan Computer
* Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
* Copyright (C) 2006,2007 AMD
* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "mcp55.h"
static void pcie_init(struct device *dev)
{
/* Enable pci error detecting */
u32 dword;
/* System error enable */
dword = pci_read_config32(dev, 0x04);
dword |= (1<<8); /* System error enable */
dword |= (1<<30); /* Clear possible errors */
pci_write_config32(dev, 0x04, dword);
}
static struct device_operations pcie_ops = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources,
.init = pcie_init,
.scan_bus = pci_scan_bridge,
// .enable = mcp55_enable,
};
static const unsigned short pcie_ids[] = {
PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_B_C,
PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_E,
PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_A,
PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_F,
PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D,
0
};
static const struct pci_driver pciebc_driver __pci_driver = {
.ops = &pcie_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.devices= pcie_ids,
};

34
src/southbridge/nvidia/mcp55/reset.c
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@ -1,34 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2004 Tyan Computer
* Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
* Copyright (C) 2006,2007 AMD
* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define __SIMPLE_DEVICE__
#include <arch/io.h>
#include <reset.h>
#include "../../../northbridge/amd/amdk8/reset_test.c"
void do_board_reset(void)
{
set_bios_reset();
/* Try rebooting through port 0xcf9 */
/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
outb((0 <<3)|(0<<2)|(1<<1), 0xcf9);
outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
}

55
src/southbridge/nvidia/mcp55/romstrap.S
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@ -1,55 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2004 Tyan Computer
* Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
.section ".romstrap", "a", @progbits
.globl __romstrap_start
__romstrap_start:
rstables:
.long 0x2b16d065
.long 0x0
.long 0x0
.long linkedlist
linkedlist:
.long 0x0003001C // 10h
.long 0x08000000 // 14h
.long 0x00000000 // 18h
.long 0xFFFFFFFF // 1Ch
.long 0xFFFFFFFF // 20h
.long 0xFFFFFFFF // 24h
.long 0xFFFFFFFF // 28h
.long 0xFFFFFFFF // 2Ch
.long 0x81543266 // 30h, MAC address low 4 byte ---> keep it in 0xffffffd0
.long 0x000000E0 // 34h, MAC address high 4 byte
.long 0x002309CE // 38h, UUID low 4 byte
.long 0x00E08100 // 3Ch, UUID high 4 byte
rspointers:
.long rstables // It will be 0xffffffe0
.long rstables
.long rstables
.long rstables
.globl __romstrap_end
__romstrap_end:
.previous

23
src/southbridge/nvidia/mcp55/romstrap.ld
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@ -1,23 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 AMD
* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
SECTIONS {
. = (0xffffffff - 0x10) - (__romstrap_end - __romstrap_start) + 1;
.romstrap (.): {
KEEP(*(.romstrap))
}
}

89
src/southbridge/nvidia/mcp55/sata.c
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@ -1,89 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2004 Tyan Computer
* Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
* Copyright (C) 2006,2007 AMD
* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "chip.h"
#include "mcp55.h"
static void sata_init(struct device *dev)
{
u32 dword;
struct southbridge_nvidia_mcp55_config *conf;
conf = dev->chip_info;
dword = pci_read_config32(dev, 0x50);
/* Ensure prefetch is disabled */
dword &= ~((1 << 15) | (1 << 13));
if (conf) {
if (conf->sata1_enable) {
/* Enable secondary SATA interface */
dword |= (1<<0);
printk(BIOS_DEBUG, "SATA S\t");
}
if (conf->sata0_enable) {
/* Enable primary SATA interface */
dword |= (1<<1);
printk(BIOS_DEBUG, "SATA P\n");
}
} else {
dword |= (1<<1) | (1<<0);
printk(BIOS_DEBUG, "SATA P and S\n");
}
#if 1
dword &= ~(0x1f<<24);
dword |= (0x15<<24);
#endif
pci_write_config32(dev, 0x50, dword);
dword = pci_read_config32(dev, 0xf8);
dword |= 2;
pci_write_config32(dev, 0xf8, dword);
}
static struct device_operations sata_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
// .enable = mcp55_enable,
.init = sata_init,
.scan_bus = 0,
.ops_pci = &mcp55_pci_ops,
};
static const struct pci_driver sata0_driver __pci_driver = {
.ops = &sata_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_MCP55_SATA0,
};
static const struct pci_driver sata1_driver __pci_driver = {
.ops = &sata_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_MCP55_SATA1,
};

132
src/southbridge/nvidia/mcp55/smbus.c
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@ -1,132 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2004 Tyan Computer
* Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
* Copyright (C) 2006,2007 AMD
* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/smbus.h>
#include "mcp55.h"
#include "smbus.h"
static int lsmbus_recv_byte(struct device *dev)
{
unsigned int device;
struct resource *res;
struct bus *pbus;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4));
return do_smbus_recv_byte(res->base, device);
}
static int lsmbus_send_byte(struct device *dev, u8 val)
{
unsigned int device;
struct resource *res;
struct bus *pbus;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4));
return do_smbus_send_byte(res->base, device, val);
}
static int lsmbus_read_byte(struct device *dev, u8 address)
{
unsigned int device;
struct resource *res;
struct bus *pbus;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4));
return do_smbus_read_byte(res->base, device, address);
}
static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
{
unsigned int device;
struct resource *res;
struct bus *pbus;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4));
return do_smbus_write_byte(res->base, device, address, val);
}
static struct smbus_bus_operations lops_smbus_bus = {
.recv_byte = lsmbus_recv_byte,
.send_byte = lsmbus_send_byte,
.read_byte = lsmbus_read_byte,
.write_byte = lsmbus_write_byte,
};
#if CONFIG(HAVE_ACPI_TABLES)
unsigned int pm_base;
#endif
static void mcp55_sm_read_resources(struct device *dev)
{
unsigned long index;
/* Get the normal pci resources of this device */
pci_dev_read_resources(dev);
for (index = 0x60; index <= 0x68; index+=4) { // We got another 3.
pci_get_resource(dev, index);
}
compact_resources(dev);
}
static void mcp55_sm_init(struct device *dev)
{
#if CONFIG(HAVE_ACPI_TABLES)
struct resource *res;
res = find_resource(dev, 0x60);
if (res)
pm_base = res->base;
#endif
}
static struct device_operations smbus_ops = {
.read_resources = mcp55_sm_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = mcp55_sm_init,
.scan_bus = scan_smbus,
// .enable = mcp55_enable,
.ops_pci = &mcp55_pci_ops,
.ops_smbus_bus = &lops_smbus_bus,
};
static const struct pci_driver smbus_driver __pci_driver = {
.ops = &smbus_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_MCP55_SM2,
};

173
src/southbridge/nvidia/mcp55/smbus.h
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@ -1,173 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2004 Tyan Computer
* Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
* Copyright (C) 2006,2007 AMD
* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <device/smbus_def.h>
#define SMBHSTSTAT 0x1
#define SMBHSTPRTCL 0x0
#define SMBHSTCMD 0x3
#define SMBXMITADD 0x2
#define SMBHSTDAT0 0x4
#define SMBHSTDAT1 0x5
/* Between 1-10 seconds, We should never timeout normally
* Longer than this is just painful when a timeout condition occurs.
*/
#define SMBUS_TIMEOUT (100*1000*10)
static inline void smbus_delay(void)
{
outb(0x80, 0x80);
}
static int smbus_wait_until_done(unsigned int smbus_io_base)
{
unsigned long loops;
loops = SMBUS_TIMEOUT;
do {
unsigned char val;
smbus_delay();
val = inb(smbus_io_base + SMBHSTSTAT);
if ((val & 0xff) != 0) {
return 0;
}
} while (--loops);
return -3;
}
static int do_smbus_recv_byte(unsigned int smbus_io_base, unsigned int device)
{
unsigned char global_status_register;
unsigned char byte;
/* set the device I'm talking to */
outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD);
smbus_delay();
/* byte data recv */
outb(0x05, smbus_io_base + SMBHSTPRTCL);
smbus_delay();
/* poll for transaction completion */
if (smbus_wait_until_done(smbus_io_base) < 0) {
return -3;
}
global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */
/* read results of transaction */
byte = inb(smbus_io_base + SMBHSTCMD);
if (global_status_register != 0x80) { // lose check, otherwise it should be 0
return -1;
}
return byte;
}
static int do_smbus_send_byte(unsigned int smbus_io_base, unsigned int device, unsigned char val)
{
unsigned int global_status_register;
outb(val, smbus_io_base + SMBHSTDAT0);
smbus_delay();
/* set the command... */
outb(val, smbus_io_base + SMBHSTCMD);
smbus_delay();
/* set the device I'm talking to */
outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD);
smbus_delay();
/* set up for a byte data write */
outb(0x04, smbus_io_base + SMBHSTPRTCL);
smbus_delay();
/* poll for transaction completion */
if (smbus_wait_until_done(smbus_io_base) < 0) {
return -3;
}
global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */
if (global_status_register != 0x80) {
return -1;
}
return 0;
}
static int do_smbus_read_byte(unsigned int smbus_io_base, unsigned int device, unsigned int address)
{
unsigned char global_status_register;
unsigned char byte;
/* set the device I'm talking to */
outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD);
smbus_delay();
/* set the command/address... */
outb(address & 0xff, smbus_io_base + SMBHSTCMD);
smbus_delay();
/* byte data read */
outb(0x07, smbus_io_base + SMBHSTPRTCL);
smbus_delay();
/* poll for transaction completion */
if (smbus_wait_until_done(smbus_io_base) < 0) {
return -3;
}
global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */
/* read results of transaction */
byte = inb(smbus_io_base + SMBHSTDAT0);
if (global_status_register != 0x80) { // lose check, otherwise it should be 0
return -1;
}
return byte;
}
static int do_smbus_write_byte(unsigned int smbus_io_base, unsigned int device, unsigned int address, unsigned char val)
{
unsigned int global_status_register;
outb(val, smbus_io_base + SMBHSTDAT0);
smbus_delay();
/* set the device I'm talking to */
outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD);
smbus_delay();
outb(address & 0xff, smbus_io_base + SMBHSTCMD);
smbus_delay();
/* set up for a byte data write */
outb(0x06, smbus_io_base + SMBHSTPRTCL);
smbus_delay();
/* poll for transaction completion */
if (smbus_wait_until_done(smbus_io_base) < 0) {
return -3;
}
global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */
if (global_status_register != 0x80) {
return -1;
}
return 0;
}

39
src/southbridge/nvidia/mcp55/usb.c
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@ -1,39 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2004 Tyan Computer
* Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
* Copyright (C) 2006,2007 AMD
* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include "mcp55.h"
static struct device_operations usb_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = 0,
// .enable = mcp55_enable,
.scan_bus = 0,
.ops_pci = &mcp55_pci_ops,
};
static const struct pci_driver usb_driver __pci_driver = {
.ops = &usb_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_MCP55_USB,
};

49
src/southbridge/nvidia/mcp55/usb2.c
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@ -1,49 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2004 Tyan Computer
* Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
* Copyright (C) 2006,2007 AMD
* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "mcp55.h"
#include <device/pci_ehci.h>
static void usb2_init(struct device *dev)
{
u32 dword;
dword = pci_read_config32(dev, 0xf8);
dword |= 40;
pci_write_config32(dev, 0xf8, dword);
}
static struct device_operations usb2_ops = {
.read_resources = pci_ehci_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = usb2_init,
// .enable = mcp55_enable,
.scan_bus = 0,
.ops_pci = &mcp55_pci_ops,
};
static const struct pci_driver usb2_driver __pci_driver = {
.ops = &usb2_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_MCP55_USB2,
};