mb/lenovo/t520: Disable SATA2 and Thermal on W520

If a discoverable device (e.g. a PCI device) does not appear in the
devicetree (typically because it is removable), coreboot enables it
by default. Disable the SATA2 (device for SATA ports 4 and 5, which
is not used in AHCI mode) and Thermal devices on W520 as well. Both
devices were only disabled on the T520.

Tested, this change fixes a long boot time when using MrChromebox's
edk2 payload on the W520, likely related to the following errors:

    AHCI: Error interrupt reported PxIS: 40000001
    Non data transfer failed at retry 0
    AHCI: Error interrupt reported PxIS: 40000001
    Non data transfer failed at retry 1
    AHCI: Error interrupt reported PxIS: 40000001
    Non data transfer failed at retry 2
    AHCI: Error interrupt reported PxIS: 40000001
    Non data transfer failed at retry 3
    AHCI: Error interrupt reported PxIS: 40000001
    Non data transfer failed at retry 4

Change-Id: I0b0483aae05fa84d97987a93db634b740f830e18
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71857
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2023-01-12 15:52:55 +01:00 committed by Felix Held
parent 9ed576fbcd
commit 1cb930b5d1
2 changed files with 2 additions and 2 deletions

View File

@ -145,6 +145,8 @@ chip northbridge/intel/sandybridge
device i2c 5f on end device i2c 5f on end
end end
end # SMBus end # SMBus
device pci 1f.5 off end # IDE controller
device pci 1f.6 off end # Thermal controller
end end
end end
end end

View File

@ -9,8 +9,6 @@ chip northbridge/intel/sandybridge
register "wwan_gpio_lvl" = "0" register "wwan_gpio_lvl" = "0"
end end
end # LPC bridge end # LPC bridge
device pci 1f.5 off end # IDE controller
device pci 1f.6 off end # Thermal controller
end end
end end
end end