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Drop ROMCC code and header guards 

Change-Id: I730f80afd8aad250f26534435aec24bea75a849c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
This commit is contained in:
Arthur Heymans 2019-11-28 16:05:08 +01:00 committed by Kyösti Mälkki
parent 4f66cb9b28
commit 1cb9cd5798
35 changed files with 13 additions and 299 deletions
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25
src/arch/x86/assembly_entry.S
View File

@ -13,8 +13,6 @@
#include <rules.h>
#if !CONFIG(ROMCC_BOOTBLOCK)
/*
* This path is for stages that are post bootblock. The gdt is reloaded
* to accommodate platforms that are executing out of CAR. In order to
@ -60,26 +58,3 @@ debug_spinloop:
/* Expect to never return. */
1:
jmp 1b
#else
/* This file assembles the start of the romstage program by the order of the
* includes. Thus, it's extremely important that one pays very careful
* attention to the order of the includes. */
#include <arch/x86/prologue.inc>
#include <cpu/x86/32bit/entry32.inc>
#include <cpu/x86/fpu_enable.inc>
#if CONFIG(SSE)
#include <cpu/x86/sse_enable.inc>
#endif
/*
* The assembly.inc is generated based on the requirements of the mainboard.
* For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be
* processed by ROMCC and added. In non-ROMCC boards the chipsets'
* cache-as-ram setup files would be here.
*/
#include <generated/assembly.inc>
#endif

2
src/arch/x86/c_start.S
View File

@ -148,7 +148,7 @@ gdtaddr:
.data
/* This is the gdt for GCC part of coreboot.
* It is different from the gdt in ROMCC/ASM part of coreboot
* It is different from the gdt in ASM part of coreboot
* which is defined in entry32.inc
*
* When the machine is initially started, we use a very simple

2
src/arch/x86/include/arch/acpi.h
View File

@ -45,7 +45,7 @@
#define ACPI_TABLE_CREATOR "COREBOOT" /* Must be exactly 8 bytes long! */
#define OEM_ID "COREv4" /* Must be exactly 6 bytes long! */
#if !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMCC__)
#if !defined(__ASSEMBLER__) && !defined(__ACPI__)
#include <commonlib/helpers.h>
#include <device/device.h>
#include <uuid.h>

9
src/arch/x86/include/arch/cpu.h
View File

@ -218,9 +218,6 @@ static inline bool cpu_is_intel(void)
return CONFIG(CPU_INTEL_COMMON) || CONFIG(SOC_INTEL_COMMON);
}
#ifndef __ROMCC__
/* romcc does not support anonymous structs. */
struct device;
struct cpu_device_id {
@ -288,13 +285,11 @@ static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
#define asmlinkage __attribute__((regparm(0)))
/*
* When not using a romcc bootblock the car_stage_entry() is the symbol
* jumped to for each stage after bootblock using cache-as-ram.
* The car_stage_entry() is the symbol jumped to for each stage
* after bootblock using cache-as-ram.
*/
asmlinkage void car_stage_entry(void);
#endif
/*
* Get processor id using cpuid eax=1
* return value in EAX register

7
src/arch/x86/include/arch/hlt.h
View File

@ -14,16 +14,9 @@
#ifndef ARCH_HLT_H
#define ARCH_HLT_H
#if defined(__ROMCC__)
static void hlt(void)
{
__builtin_hlt();
}
#else
static __always_inline void hlt(void)
{
asm("hlt");
}
#endif
#endif /* ARCH_HLT_H */

34
src/arch/x86/include/arch/io.h
View File

@ -21,39 +21,6 @@
* inb/inw/inl/outb/outw/outl and the "string versions" of the same
* (insb/insw/insl/outsb/outsw/outsl).
*/
#if defined(__ROMCC__)
static inline void outb(uint8_t value, uint16_t port)
{
__builtin_outb(value, port);
}
static inline void outw(uint16_t value, uint16_t port)
{
__builtin_outw(value, port);
}
static inline void outl(uint32_t value, uint16_t port)
{
__builtin_outl(value, port);
}
static inline uint8_t inb(uint16_t port)
{
return __builtin_inb(port);
}
static inline uint16_t inw(uint16_t port)
{
return __builtin_inw(port);
}
static inline uint32_t inl(uint16_t port)
{
return __builtin_inl(port);
}
#else
static inline void outb(uint8_t value, uint16_t port)
{
__asm__ __volatile__ ("outb %b0, %w1" : : "a" (value), "Nd" (port));
@ -89,7 +56,6 @@ static inline uint32_t inl(uint16_t port)
__asm__ __volatile__ ("inl %w1, %0" : "=a"(value) : "Nd" (port));
return value;
}
#endif /* __ROMCC__ */
static inline void outsb(uint16_t port, const void *addr, unsigned long count)
{

4
src/arch/x86/include/arch/mmio.h
View File

@ -34,13 +34,11 @@ static __always_inline uint32_t read32(
return *((volatile uint32_t *)(addr));
}
#ifndef __ROMCC__
static __always_inline uint64_t read64(
const volatile void *addr)
{
return *((volatile uint64_t *)(addr));
}
#endif
static __always_inline void write8(volatile void *addr,
uint8_t value)
@ -60,12 +58,10 @@ static __always_inline void write32(volatile void *addr,
*((volatile uint32_t *)(addr)) = value;
}
#ifndef __ROMCC__
static __always_inline void write64(volatile void *addr,
uint64_t value)
{
*((volatile uint64_t *)(addr)) = value;
}
#endif
#endif /* __ARCH_MMIO_H__ */

70
src/arch/x86/include/arch/pci_mmio_cfg_romcc.h
View File

@ -1,70 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _PCI_MMIO_CFG_ROMCC_H
#define _PCI_MMIO_CFG_ROMCC_H
#include <stdint.h>
#include <device/mmio.h>
#include <device/pci_type.h>
static __always_inline
uint8_t pci_mmio_read_config8(pci_devfn_t dev, uint16_t reg)
{
void *addr;
addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | reg);
return read8(addr);
}
static __always_inline
uint16_t pci_mmio_read_config16(pci_devfn_t dev, uint16_t reg)
{
void *addr;
addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~1));
return read16(addr);
}
static __always_inline
uint32_t pci_mmio_read_config32(pci_devfn_t dev, uint16_t reg)
{
void *addr;
addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~3));
return read32(addr);
}
static __always_inline
void pci_mmio_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value)
{
void *addr;
addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | reg);
write8(addr, value);
}
static __always_inline
void pci_mmio_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value)
{
void *addr;
addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~1));
write16(addr, value);
}
static __always_inline
void pci_mmio_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value)
{
void *addr;
addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~3));
write32(addr, value);
}
#endif /* _PCI_MMIO_CFG_ROMCC_H */

6
src/arch/x86/include/arch/pci_ops.h
View File

@ -15,12 +15,6 @@
#define ARCH_I386_PCI_OPS_H
#include <arch/pci_io_cfg.h>
#if defined(__ROMCC__)
/* Must come before <device/pci_mmio_cfg.h> */
#include <arch/pci_mmio_cfg_romcc.h>
#endif
#include <device/pci_mmio_cfg.h>
#endif /* ARCH_I386_PCI_OPS_H */

7
src/commonlib/include/commonlib/cbfs_serialized.h
View File

@ -187,11 +187,6 @@ struct cbfs_file_attr_align {
uint32_t alignment;
} __packed;
/*
* ROMCC does not understand uint64_t, so we hide future definitions as they are
* unlikely to be ever needed from ROMCC
*/
#ifndef __ROMCC__
/*** Component sub-headers ***/
@ -236,6 +231,4 @@ struct cbfs_optionrom {
uint32_t len;
} __packed;
#endif /* __ROMCC__ */
#endif /* _CBFS_SERIALIZED_H_ */

9
src/commonlib/include/commonlib/helpers.h
View File

@ -41,13 +41,10 @@
var_a op var_b ? var_a : var_b; \
})
#ifdef __ROMCC__ /* romcc doesn't support __builtin_choose_expr() */
#define __CMP(a, b, op) __CMP_UNSAFE(a, b, op)
#else
#define __CMP(a, b, op) __builtin_choose_expr( \
__builtin_constant_p(a) && __builtin_constant_p(b), \
__CMP_UNSAFE(a, b, op), __CMP_SAFE(a, b, op, __TMPNAME, __TMPNAME))
#endif
#ifndef MIN
#define MIN(a, b) __CMP(a, b, <)
@ -108,12 +105,8 @@
#define GHz (1000 * MHz)
#ifndef offsetof
#ifdef __ROMCC__
#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
#else
#define offsetof(TYPE, MEMBER) __builtin_offsetof(TYPE, MEMBER)
#endif
#endif
#define check_member(structure, member, offset) _Static_assert( \
offsetof(struct structure, member) == offset, \

3
src/console/die.c
View File

@ -15,8 +15,6 @@
#include <console/console.h>
#include <halt.h>
#ifndef __ROMCC__
/*
* The method should be overwritten in mainboard directory to signal that a
* fatal error had occurred. On boards that do share the same EC and where the
@ -39,4 +37,3 @@ void __noreturn die(const char *fmt, ...)
die_notify();
halt();
}
#endif

7
src/console/post.c
View File

@ -24,8 +24,6 @@
/* Write POST information */
/* someday romcc will be gone. */
#ifndef __ROMCC__
/* Some mainboards have very nice features beyond just a simple display.
* They can override this function.
*/
@ -33,11 +31,6 @@ void __weak mainboard_post(uint8_t value)
{
}
#else
/* This just keeps the number of #ifs to a minimum */
#define mainboard_post(x)
#endif
#if CONFIG(CMOS_POST)
DECLARE_SPIN_LOCK(cmos_post_lock)

3
src/cpu/x86/16bit/entry16.inc
View File

@ -29,13 +29,10 @@
#include <arch/rom_segs.h>
#if !CONFIG(ROMCC_BOOTBLOCK) || \
CONFIG(SIPI_VECTOR_IN_ROM)
/* Symbol _start16bit must be aligned to 4kB to start AP CPUs with
* Startup IPI message without RAM.
*/
.align 4096
#endif
.code16
.globl _start16bit
.type _start16bit, @function

9
src/include/console/console.h
View File

@ -26,8 +26,6 @@
#define RAM_DEBUG (CONFIG(DEBUG_RAM_SETUP) ? BIOS_DEBUG : BIOS_NEVER)
#define RAM_SPEW (CONFIG(DEBUG_RAM_SETUP) ? BIOS_SPEW : BIOS_NEVER)
#ifndef __ROMCC__
#include <console/vtxprintf.h>
void post_code(u8 value);
@ -101,11 +99,4 @@ int do_printk(int msg_level, const char *fmt, ...)
int do_vprintk(int msg_level, const char *fmt, va_list args);
#else
static inline void romcc_printk(void) { }
#define printk(...) romcc_printk()
#endif /* !__ROMCC__ */
#endif /* CONSOLE_CONSOLE_H_ */

3
src/include/console/uart.h
View File

@ -55,7 +55,6 @@ unsigned char uart_rx_byte(int idx);
uintptr_t uart_platform_base(int idx);
#if !defined(__ROMCC__)
static inline void *uart_platform_baseptr(int idx)
{
return (void *)uart_platform_base(idx);
@ -100,6 +99,4 @@ static inline u8 __gdb_rx_byte(void)
}
#endif
#endif /* __ROMCC__ */
#endif /* CONSOLE_UART_H */

2
src/include/cpu/amd/mtrr.h
View File

@ -38,7 +38,7 @@
#define TOP_MEM_MASK 0x007fffff
#define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10)
#if !defined(__ROMCC__) && !defined(__ASSEMBLER__)
#if !defined(__ASSEMBLER__)
#include <cpu/x86/msr.h>

17
src/include/cpu/x86/cache.h
View File

@ -23,28 +23,11 @@
#if !defined(__ASSEMBLER__)
/*
* Need two versions because ROMCC chokes on certain clobbers:
* cache.h:29.71: cache.h:60.24: earlymtrr.c:117.23: romstage.c:144.33:
* 0x1559920 asm Internal compiler error: lhs 1 regcm == 0
*/
#if defined(__GNUC__)
static inline void wbinvd(void)
{
asm volatile ("wbinvd" ::: "memory");
}
#else
static inline void wbinvd(void)
{
asm volatile ("wbinvd");
}
#endif
static inline void invd(void)
{
asm volatile("invd" ::: "memory");

5
src/include/cpu/x86/cr.h
View File

@ -20,12 +20,7 @@
#include <stdint.h>
/* ROMCC apparently chokes certain clobber registers. */
#if defined(__ROMCC__)
#define COMPILER_BARRIER
#else
#define COMPILER_BARRIER "memory"
#endif
#ifdef __x86_64__
#define CRx_TYPE uint64_t

16
src/include/cpu/x86/msr.h
View File

@ -81,21 +81,6 @@
#ifndef __ASSEMBLER__
#include <types.h>
#if defined(__ROMCC__)
typedef __builtin_msr_t msr_t;
static msr_t rdmsr(unsigned long index)
{
return __builtin_rdmsr(index);
}
static void wrmsr(unsigned long index, msr_t msr)
{
__builtin_wrmsr(index, msr.lo, msr.hi);
}
#else
typedef struct msr_struct {
unsigned int lo;
@ -154,7 +139,6 @@ static __always_inline void wrmsr(unsigned int index, msr_t msr)
}
#endif /* CONFIG_SOC_SETS_MSRS */
#endif /* __ROMCC__ */
/* Helpers for interpreting MC[i]_STATUS */

6
src/include/cpu/x86/mtrr.h
View File

@ -53,7 +53,7 @@
#define MTRR_FIX_4K_F0000 0x26e
#define MTRR_FIX_4K_F8000 0x26f
#if !defined(__ASSEMBLER__) && !defined(__ROMCC__)
#if !defined(__ASSEMBLER__)
#include <stdint.h>
#include <stddef.h>
@ -140,9 +140,9 @@ static inline unsigned int fls(unsigned int x)
"1:" : "=r" (r) : "mr" (x));
return r;
}
#endif /* !defined(__ASSEMBLER__) && !defined(__ROMCC__) */
#endif /* !defined(__ASSEMBLER__) */
/* Align up/down to next power of 2, suitable for ROMCC and assembler
/* Align up/down to next power of 2, suitable for assembler
too. Range of result 256kB to 128MB is good enough here. */
#define _POW2_MASK(x) ((x>>1)|(x>>2)|(x>>3)|(x>>4)|(x>>5)| \
(x>>6)|(x>>7)|(x>>8)|((1<<18)-1))

3
src/include/cpu/x86/tsc.h
View File

@ -28,7 +28,6 @@ static inline tsc_t rdtsc(void)
return res;
}
#if !defined(__ROMCC__)
/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow.
* This code is used to prevent use of libgcc's umoddi3.
*/
@ -42,7 +41,6 @@ static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b)
tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16);
}
/* Too many registers for ROMCC */
static inline unsigned long long rdtscll(void)
{
unsigned long long val;
@ -58,7 +56,6 @@ static inline uint64_t tsc_to_uint64(tsc_t tstamp)
{
return (((uint64_t)tstamp.hi) << 32) + tstamp.lo;
}
#endif
/* Provided by CPU/chipset code for the TSC rate in MHz. */
unsigned long tsc_freq_mhz(void);

9
src/include/device/device.h
View File

@ -2,13 +2,6 @@
#define DEVICE_H
/*
* NOTICE: Header is ROMCC tentative.
* This header is incompatible with ROMCC and its inclusion leads to 'odd'
* build failures.
*/
#if !defined(__ROMCC__)
#include <device/resource.h>
#include <device/path.h>
#include <device/pci_type.h>
@ -330,6 +323,4 @@ void scan_smbus(struct device *bus);
void scan_generic_bus(struct device *bus);
void scan_static_bus(struct device *bus);
#endif /* !defined(__ROMCC__) */
#endif /* DEVICE_H */

3
src/include/device/mmio.h
View File

@ -37,7 +37,6 @@
#define clrbits32(addr, clear) clrsetbits32(addr, clear, 0)
#define clrbits64(addr, clear) clrsetbits64(addr, clear, 0)
#ifndef __ROMCC__
/*
* Reads a transfer buffer from 32-bit FIFO registers. fifo_stride is the
* distance in bytes between registers (e.g. pass 4 for a normal array of 32-bit
@ -195,6 +194,4 @@ static inline void buffer_to_fifo32(void *buffer, size_t size, void *fifo,
#define READ32_BITFIELD(addr, name) \
EXTRACT_BITFIELD(read32(addr), name)
#endif /* !__ROMCC__ */
#endif /* __DEVICE_MMIO_H__ */

3
src/include/device/pci_mmio_cfg.h
View File

@ -20,7 +20,6 @@
#include <device/mmio.h>
#include <device/pci_type.h>
#if !defined(__ROMCC__)
/* By not assigning this to CONFIG_MMCONF_BASE_ADDRESS here we
* prevent some sub-optimal constant folding. */
@ -110,8 +109,6 @@ uint32_t *pci_mmio_config32_addr(pci_devfn_t dev, uint16_t reg)
return (uint32_t *)&pcicfg(dev)->reg32[reg / sizeof(uint32_t)];
}
#endif /* !defined(__ROMCC__) */
#if CONFIG(MMCONF_SUPPORT)
#if CONFIG_MMCONF_BASE_ADDRESS == 0

4
src/include/device/pci_ops.h
View File

@ -23,7 +23,6 @@
#include <device/pci_type.h>
#include <arch/pci_ops.h>
#ifndef __ROMCC__
void __noreturn pcidev_die(void);
static __always_inline pci_devfn_t pcidev_bdf(const struct device *dev)
@ -37,7 +36,6 @@ static __always_inline pci_devfn_t pcidev_assert(const struct device *dev)
pcidev_die();
return pcidev_bdf(dev);
}
#endif
#if defined(__SIMPLE_DEVICE__)
#define ENV_PCI_SIMPLE_DEVICE 1
@ -184,7 +182,6 @@ void pci_update_config32(const struct device *dev, u16 reg, u32 mask, u32 or)
u16 pci_s_find_next_capability(pci_devfn_t dev, u16 cap, u16 last);
u16 pci_s_find_capability(pci_devfn_t dev, u16 cap);
#ifndef __ROMCC__
static __always_inline
u16 pci_find_next_capability(const struct device *dev, u16 cap, u16 last)
{
@ -196,6 +193,5 @@ u16 pci_find_capability(const struct device *dev, u16 cap)
{
return pci_s_find_capability(PCI_BDF(dev), cap);
}
#endif
#endif /* PCI_OPS_H */

2
src/include/endian.h
View File

@ -79,7 +79,6 @@
#define clrsetbits_le16(addr, clear, set) __clrsetbits(le, 16, addr, clear, set)
#define clrsetbits_be16(addr, clear, set) __clrsetbits(be, 16, addr, clear, set)
#ifndef __ROMCC__
/* be16dec/be32dec/be64dec/le16dec/le32dec/le64dec family of functions. */
#define DEFINE_ENDIAN_DEC(endian, width) \
static inline uint##width##_t endian##width##dec(const void *p) \
@ -169,6 +168,5 @@ static inline uint64_t le64toh(uint64_t little_endian_64bits)
{
return le64_to_cpu(little_endian_64bits);
}
#endif
#endif

4
src/include/halt.h
View File

@ -17,14 +17,10 @@
#ifndef __HALT_H__
#define __HALT_H__
#ifdef __ROMCC__
#include <lib/halt.c>
#else
/**
* halt the system reliably
*/
void __noreturn halt(void);
#endif /* __ROMCC__ */
/* Power off the system. */
void poweroff(void);

2
src/include/lib.h
View File

@ -57,14 +57,12 @@ void hexdump32(char LEVEL, const void *d, size_t len);
*/
size_t hexstrtobin(const char *str, uint8_t *buf, size_t len);
#if !defined(__ROMCC__)
/* Count Leading Zeroes: clz(0) == 32, clz(0xf) == 28, clz(1 << 31) == 0 */
static inline int clz(u32 x) { return x ? __builtin_clz(x) : sizeof(x) * 8; }
/* Integer binary logarithm (rounding down): log2(0) == -1, log2(5) == 2 */
static inline int log2(u32 x) { return sizeof(x) * 8 - clz(x) - 1; }
/* Find First Set: __ffs(1) == 0, __ffs(0) == -1, __ffs(1<<31) == 31 */
static inline int __ffs(u32 x) { return log2(x & (u32)(-(s32)x)); }
#endif
/* Integer binary logarithm (rounding up): log2_ceil(0) == -1, log2(5) == 3 */
static inline int log2_ceil(u32 x) { return (x == 0) ? -1 : log2(x * 2 - 1); }

5
src/include/stdbool.h
View File

@ -5,11 +5,8 @@
#include <stdint.h>
#ifdef __ROMCC__
typedef uint8_t bool;
#else
typedef _Bool bool;
#endif
#define true 1
#define false 0

2
src/include/stddef.h
View File

@ -47,12 +47,10 @@ typedef unsigned int wint_t;
#define MAYBE_STATIC_BSS
#endif
#ifndef __ROMCC__
/* Provide a pointer to address 0 that thwarts any "accessing this is
* undefined behaviour and do whatever" trickery in compilers.
* Use when you _really_ need to read32(zeroptr) (ie. read address 0).
*/
extern char zeroptr[];
#endif
#endif /* STDDEF_H */

12
src/include/stdint.h
View File

@ -28,17 +28,14 @@ typedef unsigned short uint16_t;
typedef signed int int32_t;
typedef unsigned int uint32_t;
#ifndef __ROMCC__
typedef signed long long int64_t;
typedef unsigned long long uint64_t;
#endif
/* Types for 'void *' pointers */
typedef signed long intptr_t;
typedef unsigned long uintptr_t;
/* Ensure that the widths are all correct */
#ifndef __ROMCC__
_Static_assert(sizeof(int8_t) == 1, "Size of int8_t is incorrect");
_Static_assert(sizeof(uint8_t) == 1, "Size of uint8_t is incorrect");
@ -53,13 +50,10 @@ _Static_assert(sizeof(uint64_t) == 8, "Size of uint64_t is incorrect");
_Static_assert(sizeof(intptr_t) == sizeof(void *), "Size of intptr_t is incorrect");
_Static_assert(sizeof(uintptr_t) == sizeof(void *), "Size of uintptr_t is incorrect");
#endif
/* Maximum width integer types */
#ifndef __ROMCC__
typedef int64_t intmax_t;
typedef uint64_t uintmax_t;
#endif
/* Convenient typedefs */
typedef int8_t s8;
@ -71,10 +65,8 @@ typedef uint16_t u16;
typedef int32_t s32;
typedef uint32_t u32;
#ifndef __ROMCC__
typedef int64_t s64;
typedef uint64_t u64;
#endif
/* Limits of integer types */
#define INT8_MIN ((int8_t)0x80)
@ -89,16 +81,12 @@ typedef uint64_t u64;
#define INT32_MAX ((int32_t)0x7FFFFFFF)
#define UINT32_MAX ((uint32_t)0xFFFFFFFF)
#ifndef __ROMCC__
#define INT64_MIN ((int64_t)0x8000000000000000)
#define INT64_MAX ((int64_t)0x7FFFFFFFFFFFFFFF)
#define UINT64_MAX ((uint64_t)0xFFFFFFFFFFFFFFFF)
#endif
#ifndef __ROMCC__
#define INTMAX_MIN INT64_MIN
#define INTMAX_MAX INT64_MAX
#define UINTMAX_MAX UINT64_MAX
#endif
#endif /* STDINT_H */

4
src/include/string.h
View File

@ -4,9 +4,7 @@
#include <stddef.h>
#include <stdlib.h>
#if !defined(__ROMCC__)
#include <console/vtxprintf.h>
#endif
/* Stringify a token */
#ifndef STRINGIFY
@ -19,10 +17,8 @@ void *memmove(void *dest, const void *src, size_t n);
void *memset(void *s, int c, size_t n);
int memcmp(const void *s1, const void *s2, size_t n);
void *memchr(const void *s, int c, size_t n);
#if !defined(__ROMCC__)
int snprintf(char *buf, size_t size, const char *fmt, ...);
int vsnprintf(char *buf, size_t size, const char *fmt, va_list args);
#endif
char *strdup(const char *s);
char *strconcat(const char *s1, const char *s2);
size_t strnlen(const char *src, size_t max);

6
src/include/swab.h
View File

@ -21,7 +21,7 @@
#include <stdint.h>
#if defined(__ROMCC__) || ENV_ARMV4
#if ENV_ARMV4
#define swab16(x) \
((unsigned short)( \
(((unsigned short)(x) & (unsigned short)0x00ffU) << 8) | \
@ -44,10 +44,10 @@
(((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \
(((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \
(((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56)))
#else /* __ROMCC__ || ENV_ARMV4 */
#else /* ENV_ARMV4 */
#define swab16(x) ((uint16_t)__builtin_bswap16(x))
#define swab32(x) ((uint32_t)__builtin_bswap32(x))
#define swab64(x) ((uint64_t)__builtin_bswap64(x))
#endif /* !(__ROMCC__ || ENV_ARMV4) */
#endif /* !ENV_ARMV4 */
#endif /* _SWAB_H */

7
src/vendorcode/eltan/security/verified_boot/vboot_check.c
View File

@ -276,13 +276,6 @@ void verified_boot_early_check(void)
{
printk(BIOS_SPEW, "%s: processing early items\n", __func__);
if (CONFIG(ROMCC_BOOTBLOCK) &&
CONFIG(VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST)) {
printk(BIOS_SPEW, "%s: check the manifest\n", __func__);
if (verified_boot_check_manifest() != 0)
die("invalid manifest");
}
if (CONFIG(VENDORCODE_ELTAN_MBOOT)) {
printk(BIOS_DEBUG, "mb_measure returned 0x%x\n",
mb_measure(vboot_platform_is_resuming()));