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Add MMCONF resource to AMD fam15tn PCI_DOMAIN 

In the process of verifying change it was discovered the MMCONF
default base address 0xA0000000 was set below mem_top 0xE0000000
and bus number 256 wasn't a relistic number. The Kconfig defaults were
changed to mirror fam15 defaults base address 0xF8000000 and bus
number 64. Verified changes with boot to OS.

This is a port of the following:
commit d5c998be99

	The coreboot resource allocator doesn't respect resources
	claimed in the APIC_CLUSTER. Move the MMCONF resource to the
	PCI_DOMAIN to prevent overlap with PCI devices.

original-Change-Id: I8541795f69bbdd9041b390103fb901d37e07eeb9
    Signed-off-by: Marc Jones <marc.jones@se-eng.com
    URL - http://review.coreboot.org/#/c/2167/

Change-Id: I47660061538f8889f528b9b880a82645074886a7
Signed-off-by: Steven Sherk <steven.sherk@se-eng.com>
Reviewed-on: http://review.coreboot.org/2260
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is contained in:
Steven Sherk 2013-02-01 09:22:35 -07:00 committed by Marc Jones
parent 17aed02048
commit 1cbabb00d9
2 changed files with 21 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/northbridge/amd/agesa/family15tn/Kconfig
View File

@ -33,10 +33,10 @@ config HW_MEM_HOLE_SIZE_AUTO_INC
config MMCONF_BASE_ADDRESS config MMCONF_BASE_ADDRESS
hex hex
default 0xA0000000 default 0xF8000000
config MMCONF_BUS_NUMBER config MMCONF_BUS_NUMBER
int int
default 256 default 64
endif endif

31
src/northbridge/amd/agesa/family15tn/northbridge.c
View File

@ -337,6 +337,19 @@ static void nb_read_resources(device_t dev)
amdfam15_link_read_bases(dev, nodeid, link->link_num); amdfam15_link_read_bases(dev, nodeid, link->link_num);
} }
} }
/*
* This MMCONF resource must be reserved in the PCI_DOMAIN.
* It is not honored by the coreboot resource allocator if it is in
* the APIC_CLUSTER.
*/
#if CONFIG_MMCONF_SUPPORT
struct resource *resource = new_resource(dev, 0xc0010058);
resource->base = CONFIG_MMCONF_BASE_ADDRESS;
resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
#endif
} }
static void set_resource(device_t dev, struct resource *resource, u32 nodeid) static void set_resource(device_t dev, struct resource *resource, u32 nodeid)
@ -440,6 +453,12 @@ static void nb_set_resources(device_t dev)
assign_resources(bus); assign_resources(bus);
} }
} }
/* Print the MMCONF region if it has been reserved. */
res = find_resource(dev, 0xc0010058);
if (res) {
report_resource_stored(dev, res, " <mmconfig>");
}
} }
static void northbridge_init(struct device *dev) static void northbridge_init(struct device *dev)
@ -1077,22 +1096,10 @@ static void cpu_bus_noop(device_t dev)
static void cpu_bus_read_resources(device_t dev) static void cpu_bus_read_resources(device_t dev)
{ {
#if CONFIG_MMCONF_SUPPORT
struct resource *resource = new_resource(dev, 0xc0010058);
resource->base = CONFIG_MMCONF_BASE_ADDRESS;
resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
#endif
} }
static void cpu_bus_set_resources(device_t dev) static void cpu_bus_set_resources(device_t dev)
{ {
struct resource *resource = find_resource(dev, 0xc0010058);
if (resource) {
report_resource_stored(dev, resource, " <mmconfig>");
}
pci_dev_set_resources(dev);
} }
static struct device_operations cpu_bus_ops = { static struct device_operations cpu_bus_ops = {