GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Use defines for some i82801ex/gx registers 

Change-Id: I0069ec26278b82d61ce5bcfb94d77647dfd3254b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/2530
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2013-02-26 19:21:39 +02:00 committed by Stefan Reinauer
parent 8f4647a24b
commit 1cca340942
4 changed files with 12 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
src/southbridge/intel/i82801ex/i82801ex.h
View File

@ -12,4 +12,11 @@ extern void i82801ex_enable(device_t dev);
#define RTC_CONF 0xd8 #define RTC_CONF 0xd8
#define GEN_PMCON_3 0xa4 #define GEN_PMCON_3 0xa4
#define PMBASE 0x40
#define ACPI_CNTL 0x44
#define ACPI_EN (1 << 4)
#define GPIO_BASE 0x58
#define GPIO_CNTL 0x5C
#define GPIO_EN (1 << 4)
#endif /* I82801EX_H */ #endif /* I82801EX_H */

8
src/southbridge/intel/i82801ex/lpc.c
View File

@ -12,8 +12,6 @@
#include <arch/ioapic.h> #include <arch/ioapic.h>
#include "i82801ex.h" #include "i82801ex.h"
#define ACPI_BAR 0x40
#define GPIO_BAR 0x58
#define NMI_OFF 0 #define NMI_OFF 0
#define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_OFF 0
@ -193,7 +191,7 @@ static void i82801ex_gpio_init(device_t dev)
/* Get the chip configuration */ /* Get the chip configuration */
config = dev->chip_info; config = dev->chip_info;
/* Find the GPIO bar */ /* Find the GPIO bar */
res = find_resource(dev, GPIO_BAR); res = find_resource(dev, GPIO_BASE);
if (!res) { if (!res) {
return; return;
} }
@ -295,10 +293,10 @@ static void i82801ex_lpc_read_resources(device_t dev)
pci_dev_read_resources(dev); pci_dev_read_resources(dev);
/* Add the ACPI BAR */ /* Add the ACPI BAR */
res = pci_get_resource(dev, ACPI_BAR); res = pci_get_resource(dev, PMBASE);
/* Add the GPIO BAR */ /* Add the GPIO BAR */
res = pci_get_resource(dev, GPIO_BAR); res = pci_get_resource(dev, GPIO_BASE);
/* Add an extra subtractive resource for both memory and I/O. */ /* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));

1
src/southbridge/intel/i82801gx/i82801gx.h
View File

@ -80,6 +80,7 @@ int smbus_read_byte(unsigned device, unsigned address);
#define PMBASE 0x40 #define PMBASE 0x40
#define ACPI_CNTL 0x44 #define ACPI_CNTL 0x44
#define ACPI_EN (1 << 7)
#define BIOS_CNTL 0xDC #define BIOS_CNTL 0xDC
#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */

2
src/southbridge/intel/i82801gx/lpc.c
View File

@ -49,7 +49,7 @@ static void i82801gx_enable_apic(struct device *dev)
/* Enable ACPI I/O and power management. /* Enable ACPI I/O and power management.
* Set SCI IRQ to IRQ9 * Set SCI IRQ to IRQ9
*/ */
pci_write_config8(dev, ACPI_CNTL, 0x80); pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
*ioapic_index = 0; *ioapic_index = 0;
*ioapic_data = (1 << 25); *ioapic_data = (1 << 25);