ARMv7: Simplify div64
We don't need the overly complex optimized version, since we're only doing this in very few non-critical places. Also, add the div* files to the bootblock, they're needed if we do printk. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I83bd766d4b03b488326ade1c13b7c364a7119e7b Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2508 Tested-by: build bot (Jenkins)
This commit is contained in:
Stefan Reinauer
Ronald G. Minnich
parent
14c2398ce9
commit
1cd6160821
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@ -3,12 +3,7 @@
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#ifndef __ASM_ARM_DIV64
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#ifndef __ASM_ARM_DIV64
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#define __ASM_ARM_DIV64
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#define __ASM_ARM_DIV64
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//#include <asm/system.h>
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//#include <linux/types.h>
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// FIXME
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#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
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#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
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#define __LINUX_ARM_ARCH__ 7
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/*
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/*
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* The semantics of do_div() are:
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* The semantics of do_div() are:
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@ -34,7 +29,7 @@
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#define __xh "r1"
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#define __xh "r1"
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#endif
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#endif
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#define __do_div_asm(n, base) \
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#define do_div(n, base) \
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({ \
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({ \
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register unsigned int __base asm("r4") = base; \
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register unsigned int __base asm("r4") = base; \
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register unsigned long long __n asm("r0") = n; \
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register unsigned long long __n asm("r0") = n; \
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@ -51,183 +46,4 @@
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n = __res; \
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n = __res; \
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__rem; \
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__rem; \
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})
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})
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#if __GNUC__ < 4
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/*
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* gcc versions earlier than 4.0 are simply too problematic for the
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* optimized implementation below. First there is gcc PR 15089 that
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* tend to trig on more complex constructs, spurious .global __udivsi3
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* are inserted even if none of those symbols are referenced in the
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* generated code, and those gcc versions are not able to do constant
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* propagation on long long values anyway.
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*/
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#define do_div(n, base) __do_div_asm(n, base)
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#elif __GNUC__ >= 4
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//#include <asm/bug.h>
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/*
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* If the divisor happens to be constant, we determine the appropriate
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* inverse at compile time to turn the division into a few inline
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* multiplications instead which is much faster. And yet only if compiling
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* for ARMv4 or higher (we need umull/umlal) and if the gcc version is
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* sufficiently recent to perform proper long long constant propagation.
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* (It is unfortunate that gcc doesn't perform all this internally.)
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*/
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#define do_div(n, base) \
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({ \
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unsigned int __r, __b = (base); \
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if (!__builtin_constant_p(__b) || __b == 0 || \
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(__LINUX_ARM_ARCH__ < 4 && (__b & (__b - 1)) != 0)) { \
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/* non-constant divisor (or zero): slow path */ \
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__r = __do_div_asm(n, __b); \
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} else if ((__b & (__b - 1)) == 0) { \
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/* Trivial: __b is constant and a power of 2 */ \
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/* gcc does the right thing with this code. */ \
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__r = n; \
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__r &= (__b - 1); \
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n /= __b; \
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} else { \
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/* Multiply by inverse of __b: n/b = n*(p/b)/p */ \
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/* We rely on the fact that most of this code gets */ \
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/* optimized away at compile time due to constant */ \
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/* propagation and only a couple inline assembly */ \
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/* instructions should remain. Better avoid any */ \
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/* code construct that might prevent that. */ \
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unsigned long long __res, __x, __t, __m, __n = n; \
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unsigned int __c, __p, __z = 0; \
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/* preserve low part of n for reminder computation */ \
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__r = __n; \
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/* determine number of bits to represent __b */ \
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__p = 1 << __div64_fls(__b); \
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/* compute __m = ((__p << 64) + __b - 1) / __b */ \
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__m = (~0ULL / __b) * __p; \
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__m += (((~0ULL % __b + 1) * __p) + __b - 1) / __b; \
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/* compute __res = __m*(~0ULL/__b*__b-1)/(__p << 64) */ \
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__x = ~0ULL / __b * __b - 1; \
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__res = (__m & 0xffffffff) * (__x & 0xffffffff); \
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__res >>= 32; \
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__res += (__m & 0xffffffff) * (__x >> 32); \
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__t = __res; \
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__res += (__x & 0xffffffff) * (__m >> 32); \
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__t = (__res < __t) ? (1ULL << 32) : 0; \
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__res = (__res >> 32) + __t; \
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__res += (__m >> 32) * (__x >> 32); \
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__res /= __p; \
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/* Now sanitize and optimize what we've got. */ \
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if (~0ULL % (__b / (__b & -__b)) == 0) { \
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/* those cases can be simplified with: */ \
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__n /= (__b & -__b); \
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__m = ~0ULL / (__b / (__b & -__b)); \
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__p = 1; \
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__c = 1; \
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} else if (__res != __x / __b) { \
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/* We can't get away without a correction */ \
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/* to compensate for bit truncation errors. */ \
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/* To avoid it we'd need an additional bit */ \
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/* to represent __m which would overflow it. */ \
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/* Instead we do m=p/b and n/b=(n*m+m)/p. */ \
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__c = 1; \
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/* Compute __m = (__p << 64) / __b */ \
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__m = (~0ULL / __b) * __p; \
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__m += ((~0ULL % __b + 1) * __p) / __b; \
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} else { \
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/* Reduce __m/__p, and try to clear bit 31 */ \
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/* of __m when possible otherwise that'll */ \
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/* need extra overflow handling later. */ \
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unsigned int __bits = -(__m & -__m); \
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__bits |= __m >> 32; \
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__bits = (~__bits) << 1; \
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/* If __bits == 0 then setting bit 31 is */ \
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/* unavoidable. Simply apply the maximum */ \
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/* possible reduction in that case. */ \
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/* Otherwise the MSB of __bits indicates the */ \
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/* best reduction we should apply. */ \
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if (!__bits) { \
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__p /= (__m & -__m); \
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__m /= (__m & -__m); \
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} else { \
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__p >>= __div64_fls(__bits); \
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__m >>= __div64_fls(__bits); \
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} \
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/* No correction needed. */ \
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__c = 0; \
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} \
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/* Now we have a combination of 2 conditions: */ \
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/* 1) whether or not we need a correction (__c), and */ \
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/* 2) whether or not there might be an overflow in */ \
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/* the cross product (__m & ((1<<63) | (1<<31))) */ \
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/* Select the best insn combination to perform the */ \
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/* actual __m * __n / (__p << 64) operation. */ \
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if (!__c) { \
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asm ( "umull %Q0, %R0, %1, %Q2\n\t" \
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"mov %Q0, #0" \
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: "=&r" (__res) \
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: "r" (__m), "r" (__n) \
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: "cc" ); \
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} else if (!(__m & ((1ULL << 63) | (1ULL << 31)))) { \
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__res = __m; \
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asm ( "umlal %Q0, %R0, %Q1, %Q2\n\t" \
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"mov %Q0, #0" \
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: "+&r" (__res) \
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: "r" (__m), "r" (__n) \
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: "cc" ); \
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} else { \
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asm ( "umull %Q0, %R0, %Q1, %Q2\n\t" \
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"cmn %Q0, %Q1\n\t" \
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"adcs %R0, %R0, %R1\n\t" \
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"adc %Q0, %3, #0" \
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: "=&r" (__res) \
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: "r" (__m), "r" (__n), "r" (__z) \
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: "cc" ); \
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} \
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if (!(__m & ((1ULL << 63) | (1ULL << 31)))) { \
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asm ( "umlal %R0, %Q0, %R1, %Q2\n\t" \
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"umlal %R0, %Q0, %Q1, %R2\n\t" \
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"mov %R0, #0\n\t" \
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"umlal %Q0, %R0, %R1, %R2" \
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: "+&r" (__res) \
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: "r" (__m), "r" (__n) \
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: "cc" ); \
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} else { \
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asm ( "umlal %R0, %Q0, %R2, %Q3\n\t" \
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"umlal %R0, %1, %Q2, %R3\n\t" \
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"mov %R0, #0\n\t" \
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"adds %Q0, %1, %Q0\n\t" \
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"adc %R0, %R0, #0\n\t" \
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"umlal %Q0, %R0, %R2, %R3" \
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: "+&r" (__res), "+&r" (__z) \
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: "r" (__m), "r" (__n) \
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: "cc" ); \
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} \
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__res /= __p; \
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/* The reminder can be computed with 32-bit regs */ \
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/* only, and gcc is good at that. */ \
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{ \
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unsigned int __res0 = __res; \
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unsigned int __b0 = __b; \
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__r -= __res0 * __b0; \
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} \
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/* BUG_ON(__r >= __b || __res * __b + __r != n); */ \
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n = __res; \
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} \
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__r; \
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})
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/* our own fls implementation to make sure constant propagation is fine */
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#define __div64_fls(bits) \
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({ \
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unsigned int __left = (bits), __nr = 0; \
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if (__left & 0xffff0000) __nr += 16, __left >>= 16; \
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if (__left & 0x0000ff00) __nr += 8, __left >>= 8; \
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if (__left & 0x000000f0) __nr += 4, __left >>= 4; \
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if (__left & 0x0000000c) __nr += 2, __left >>= 2; \
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if (__left & 0x00000002) __nr += 1; \
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__nr; \
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})
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#endif
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#endif
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#endif
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@ -2,6 +2,8 @@ bootblock-y += syslib.c
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bootblock-$(CONFIG_EARLY_CONSOLE) += early_console.c
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bootblock-$(CONFIG_EARLY_CONSOLE) += early_console.c
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bootblock-y += cache_v7.c
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bootblock-y += cache_v7.c
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bootblock-y += cache-cp15.c
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bootblock-y += cache-cp15.c
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bootblock-y += div0.c
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bootblock-y += div64.S
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romstage-y += cache_v7.c
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romstage-y += cache_v7.c
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romstage-y += cache-cp15.c
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romstage-y += cache-cp15.c
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@ -13,8 +13,7 @@
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*/
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*/
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// FIXME
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// FIXME
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//#include <linux/linkage.h>
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#define __ARM_ARCH__ 7
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#define __LINUX_ARM_ARCH__ 7
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#ifdef __ARMEB__
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#ifdef __ARMEB__
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#define xh r0
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#define xh r0
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@ -65,7 +64,7 @@ __do_div64:
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@ The aligned divisor is stored in yl preserving the original.
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@ The aligned divisor is stored in yl preserving the original.
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@ The bit position is stored in ip.
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@ The bit position is stored in ip.
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#if __LINUX_ARM_ARCH__ >= 5
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#if __ARM_ARCH__ >= 5
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clz yl, r4
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clz yl, r4
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clz ip, xh
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clz ip, xh
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@ -125,7 +124,7 @@ __do_div64:
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@ We still have remainer bits in the low part. Bring them up.
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@ We still have remainer bits in the low part. Bring them up.
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#if __LINUX_ARM_ARCH__ >= 5
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#if __ARM_ARCH__ >= 5
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clz xh, xl @ we know xh is zero here so...
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clz xh, xl @ we know xh is zero here so...
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add xh, xh, #1
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add xh, xh, #1
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@ -152,7 +151,7 @@ __do_div64:
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8: @ Division by a power of 2: determine what that divisor order is
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8: @ Division by a power of 2: determine what that divisor order is
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@ then simply shift values around
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@ then simply shift values around
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#if __LINUX_ARM_ARCH__ >= 5
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#if __ARM_ARCH__ >= 5
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clz ip, r4
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clz ip, r4
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rsb ip, ip, #31
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rsb ip, ip, #31
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