From 1cf0acdc1ce54a8aa8b19378abf3075d23fa58ea Mon Sep 17 00:00:00 2001 From: Tim Van Patten Date: Thu, 15 Sep 2022 17:15:56 -0600 Subject: [PATCH] soc/amd/mendocino: Add low/no battery VRM limit registers Add DPTC Low/No battery VRM limit registers to throttle the SOC. BRANCH=none BUG=b:217911928 TEST=Build skyrim Signed-off-by: Tim Van Patten Change-Id: I9c4ed227b54efbab9f03d6acf64b1160ad73f460 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67692 Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/soc/amd/mendocino/chip.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h index 15012fd4da..0e656f5d5a 100644 --- a/src/soc/amd/mendocino/chip.h +++ b/src/soc/amd/mendocino/chip.h @@ -68,6 +68,10 @@ struct soc_amd_mendocino_config { uint32_t vrm_current_limit_mA; uint32_t vrm_maximum_current_limit_mA; uint32_t vrm_soc_current_limit_mA; + /* Throttle (e.g., Low/No Battery) */ + uint32_t vrm_current_limit_throttle_mA; + uint32_t vrm_maximum_current_limit_throttle_mA; + uint32_t vrm_soc_current_limit_throttle_mA; uint8_t smartshift_enable;