soc/intel/skylake: Add missing PCH_DEV_PCIE* definitions
This is required to add wake sources for PCIE PME events. BUG=b:37088992 Change-Id: Ideecdf133908b0819d7d993e1c7df1a6578cb77d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -111,12 +111,18 @@
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#define PCH_DEV_PCIE4 _PCH_DEV(PCIE, 3)
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#define PCH_DEV_PCIE5 _PCH_DEV(PCIE, 4)
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#define PCH_DEV_PCIE6 _PCH_DEV(PCIE, 5)
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#define PCH_DEV_PCIE7 _PCH_DEV(PCIE, 6)
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#define PCH_DEV_PCIE8 _PCH_DEV(PCIE, 7)
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#define PCH_DEV_SLOT_PCIE_1 0x1d
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#define PCH_DEVFN_PCIE9 _PCH_DEVFN(PCIE_1, 0)
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#define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1)
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#define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2)
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#define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3)
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#define PCH_DEV_PCIE9 _PCH_DEV(PCIE_1, 0)
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#define PCH_DEV_PCIE10 _PCH_DEV(PCIE_1, 1)
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#define PCH_DEV_PCIE11 _PCH_DEV(PCIE_1, 2)
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#define PCH_DEV_PCIE12 _PCH_DEV(PCIE_1, 3)
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#define PCH_DEV_SLOT_STORAGE 0x1e
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#define PCH_DEVFN_UART0 _PCH_DEVFN(STORAGE, 0)
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