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soc/amd/{picasso,common/blocks/pci}: Move populate_pirq_data 

The method now dynamically allocates the pirq structure and uses the
get_pci_routing_table method.

BUG=b:184766519
TEST=Build guybrush and verify picasso SSDT has not changed.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I297fc3ca7227fb4794ac70bd046ce2f93da8b869
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Raul E Rangel 2021-05-07 11:36:23 -06:00 committed by Felix Held
parent a8405a4c4a
commit 1d1dbc4cfa
3 changed files with 35 additions and 30 deletions
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1
src/soc/amd/common/block/include/amdblocks/amd_pci_util.h
View File

@ -51,7 +51,6 @@ struct pci_routing_info {
uint8_t irq;
} __packed;
/* Implemented by the SoC */
void populate_pirq_data(void);
/* Implemented by the SoC */

35
src/soc/amd/common/block/pci/pci_routing_info.c
View File

@ -3,6 +3,7 @@
#include <amdblocks/amd_pci_util.h>
#include <console/console.h>
#include <device/pci_def.h>
#include <stdlib.h>
#include <types.h>
enum pcie_swizzle_pin {
@ -55,3 +56,37 @@ unsigned int pci_calculate_irq(const struct pci_routing_info *routing_info,
return irq;
}
void populate_pirq_data(void)
{
const struct pci_routing_info *routing_table, *routing_entry;
size_t entries = 0;
struct pirq_struct *pirq;
unsigned int irq;
routing_table = get_pci_routing_table(&entries);
if (!routing_table || !entries)
return;
pirq = calloc(entries, sizeof(*pirq));
if (!pirq) {
printk(BIOS_ERR, "%s: Allocation failed\n", __func__);
return;
}
for (size_t i = 0; i < entries; ++i) {
routing_entry = &routing_table[i];
pirq[i].devfn = routing_entry->devfn;
for (size_t j = 0; j < 4; ++j) {
irq = pci_calculate_irq(routing_entry, j);
pirq[i].PIN[j] = irq % 8;
}
}
pirq_data_ptr = pirq;
pirq_data_size = entries;
}

29
src/soc/amd/picasso/pcie_gpp.c
View File

@ -31,35 +31,6 @@ const struct pci_routing_info *get_pci_routing_table(size_t *entries)
return pci_routing_table;
}
/*
* This data structure is populated from the raw data above. It is used
* by amd/common/block/pci/amd_pci_util to write the PCI_INT_LINE register
* to each PCI device.
*/
static struct pirq_struct pirq_data[ARRAY_SIZE(pci_routing_table)];
void populate_pirq_data(void)
{
const struct pci_routing_info *pci_routing;
struct pirq_struct *pirq;
unsigned int irq_index;
for (size_t i = 0; i < ARRAY_SIZE(pirq_data); ++i) {
pirq = &pirq_data[i];
pci_routing = &pci_routing_table[i];
pirq->devfn = pci_routing->devfn;
for (size_t j = 0; j < 4; ++j) {
irq_index = pci_calculate_irq(pci_routing, j);
pirq->PIN[j] = irq_index % 8;
}
}
pirq_data_ptr = pirq_data;
pirq_data_size = ARRAY_SIZE(pirq_data);
}
static const char *pcie_gpp_acpi_name(const struct device *dev)
{
if (dev->path.type != DEVICE_PATH_PCI)