soc/intel/common: Fix typos
Fix typos and replace spaces with tab in macro definitions. TEST=Build and Boot hatch board Change-Id: I43b2df7defc97aaeb7c8c9dfbe08ce78ba81f39b Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38384 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -106,14 +106,14 @@ heci_send(const void *msg, size_t len, uint8_t host_addr, uint8_t cse_addr);
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/*
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* Sends snd_msg of size snd_sz, and reads message into buffer pointed by
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* rcv_msg of size rcv_sz
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* Returns 0 on failure a 1 on success.
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* Returns 0 on failure and 1 on success.
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*/
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int heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, size_t *rcv_sz);
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/*
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* Attempt device reset. This is useful and perhaps only thing left to do when
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* CPU and CSE are out of sync or CSE fails to respond.
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* Returns 0 on failure a 1 on success.
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* Returns 0 on failure and 1 on success.
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*/
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int heci_reset(void);
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@ -132,14 +132,14 @@ void set_host_ready(void);
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/*
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* Polls for ME state 'HECI_OP_MODE_SEC_OVERRIDE' for 15 seconds.
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* Returns 0 on failure a 1 on success.
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* Returns 0 on failure and 1 on success.
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*/
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uint8_t wait_cse_sec_override_mode(void);
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/*
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* Sends GLOBAL_RESET_REQ cmd to CSE.The reset type can be
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* GLOBAL_RESET/HOST_RESET_ONLY/CSE_RESET_ONLY.
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* Returns -1 on failure a 0 on success.
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* Returns -1 on failure and 0 on success.
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*/
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int send_heci_reset_req_message(uint8_t rst_type);
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