amd/inagua: Drop unused Broadcom 5785 support code
Remove sample configuration code for internal Broadcom GbE device in AMD A55E aka Hudson-E1. Change-Id: Ib0262805aafc62513d9237019ade473cb1efbf1c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Kyösti Mälkki
Martin Roth
parent
813462ec31
commit
1d24b96310
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@ -27,5 +27,3 @@ romstage-y += OemCustomize.c
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ramstage-y += buildOpts.c
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ramstage-y += BiosCallOuts.c
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ramstage-y += OemCustomize.c
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ramstage-y += broadcom.c
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@ -1,358 +0,0 @@
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/*
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* Initialize Broadcom 5785 GbE MAC embedded in AMD A55E (Hudson-E1) Southbridge
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* by uploading a Selfboot Patch to the A55E's shadow ROM area. The patch
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* itself supports the Broadcom 50610(M) PHY on the AMD Inagua. It is
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* equivalent to Broadcom's SelfBoot patch V1.11 (sb5785m1.11).
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* A modified variant, selected by CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF supports
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* the Micrel KSZ9021 PHY that was used on LiPPERT FrontRunner-AF (CFR-AF)
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* revision 0v0, the first prototype. The board is history and this code now
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* serves only to document the proprietary Selfboot Patch format and how to
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* adapt it to a PHY unsupported by Broadcom.
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*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 LiPPERT ADLINK Technology GmbH
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* (Written by Jens Rottmann <JRottmann@LiPPERTembedded.de>)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <types.h>
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#include <console/console.h>
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#include <device/device.h> //coreboot device access
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#include <device/pci.h>
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#include <delay.h>
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#include <endian.h>
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void broadcom_init(void);
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#define be16(x) cpu_to_be16(x) //a little easier to type
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#define be(x) cpu_to_be32(x) //this is used a lot!
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/* C forces us to specify these before defining struct selfboot_patch :-( */
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#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF)
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#define INIT1_LENGTH 9
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#define INIT2_LENGTH 10
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#define INIT3_LENGTH 3
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#define INIT4_LENGTH 7 //this one may be 0
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#define PWRDN_LENGTH 5
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#else
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#define INIT1_LENGTH 13
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#define INIT2_LENGTH 6
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#define INIT3_LENGTH 3
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#define INIT4_LENGTH 11 //this one may be 0
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#define PWRDN_LENGTH 4
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#endif
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/* The AMD A55E (Hudson-E1) Southbridge contains an integrated Gigabit Ethernet
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* MAC, however AMD's documentation merely defines the related balls (without
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* fully describing their function) and states that only Broadcom 50610(M) PHYs
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* will be supported, that's all. The Hudson register reference skips all MAC
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* registers entirely, even AMD support doesn't seem to know more about it.
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*
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* As Broadcom refused to sell us any 50610 chips or provide any docs (or indeed
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* even a price list) below $100K expected sales we had to figure out everything
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* by ourselves. *Everything* below is the result of months of detective work,
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* documented here lest it get lost:
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*
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* The AMD A55E's GbE MAC is a Broadcom 5785, which AMD obviously licensed as IP
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* core. It uses a standard RGMII/MII interface and the Broadcom drivers will
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* recognize it by its unchanged PCI ID 14E4:1699, however there are some
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* specialties.
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*
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* The 5785 MAC can detect the link with 4 additional inputs, "phy_status[3:0]",
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* 'snooping' on the PHY's LED outputs. Interpretation of the LEDs' patterns is
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* programmed with register 0x5A4 of the MAC. AMD renamed them to "GBE_STAT" and
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* won't say anything about their purpose. Appearently hardware designers are
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* expected to blindly copy the Inagua reference schematic: GBE_STAT2:
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* 0 = activity; GBE_STAT[1:0]: 11 = no link, 10 = 10Mbit, 01 = 100Mbit, 00 = 1Gbit.
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*
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* For package processing the 5785 also features a MIPS-based RISC CPU, booting
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* from an internal ROM. The firmware loads config data and supplements (e.g. to
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* support specific PHYs), named "Selfboot Patches", via the "NVRAM Interface",
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* usually from an external EEPROM. The A55E doesn't have any balls for an ext.
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* EEPROM, instead AMD added a small internal RAM. The BIOS is expected to copy
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* the correct contents into this RAM (which only supports byte access!) upon
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* each powerup. The A55E can trigger an SMI upon writes, enabling the BIOS to
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* forward any changes to an actually 'NV' location, e.g. the BIOS's SPI flash,
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* behind the scenes. AMD calls it "GEC shadow ROM", not describing what it's
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* for nor mentioning the term "NVRAM". broadcom_init() below documents a
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* procedure how to upload the patch. No SMI magic is installed, therefore
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* 'NV'RAM writes won't be persistent.
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*
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* The "Selfboot Patch" can execute simple commands at various points during
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* main firmware execution. This can be used to change config registers,
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* initialize a specific PHY or work around firmware bugs. Broadcom provides
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* suitable Patches only for their AC131 and 50610 PHYs (as binary blobs). I
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* found them in DOS\sb_patch\5785\*\sb5785*.* in Driver_14_6_4_2.zip. (Note
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* that every 32bit-word of these files must be byte-swapped before uploading
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* them to the A55E.)
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*
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* Below is a derived Patch supporting the Micrel KSZ9021 PHY used on the
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* LiPPERT CFR-AF PC/104 SBC instead, with detailled description of the format.
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* (Here in correct order for upload.)
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*
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* This Patch made Ethernet work with Linux 3.3 - without having to modify the
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* tg3.ko driver. Broadcom's Windows-Drivers still fail with "Code 10" however;
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* disassembly showed they check the PHY ID and abort, because the Micrel PHY is
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* not supported.
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*/
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static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*!
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struct { /* Global header */
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u8 signature; //0xA5
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u8 format; //bits 7-3: patch format; 2-0: revision
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u8 mac_addr[6];
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u16 subsys_device; //IDs will be loaded into PCI config space
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u16 subsys_vendor;
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u16 pci_device; //PCI device ID; vendor is always Broadcom (0x14E4)
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u8 unknown1[8]; //?, noticed no effect
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u16 basic_config; //?, see below
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u8 checksum; //byte sum of header == 0
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u8 unknown2; //?, patch rejected if changed
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u16 patch_version; //10-8: major; 7-0: minor; 15-11: variant (1 = a, 2 = b, ...)
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} header;
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struct { /* Init code */
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u8 checksum; //byte sum of init == 0
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u8 unknown; //?, looks unused
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u8 num_hunks; //0x60 = 3 hunks, 0x80 = 4 hunks, other values not supported
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u8 size; //total size of all hunk#_code[] in bytes
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u8 hunk1_when; //mark when hunk1_code gets executed
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u8 hunk1_size; //sizeof(hunk1_code)
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u8 hunk2_when;
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u8 hunk2_size;
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u8 hunk3_when;
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u8 hunk3_size;
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u8 hunk4_when; //0x00 (padding) if only 3 hunks
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u8 hunk4_size; //dito
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u32 hunk1_code[INIT1_LENGTH]; //actual commands, see below
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u32 hunk2_code[INIT2_LENGTH];
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u32 hunk3_code[INIT3_LENGTH];
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u32 hunk4_code[INIT4_LENGTH]; //missing (zero length) if only 3 hunks
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} init;
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struct { /* Power down code */
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u8 checksum; //byte sum of powerdown == 0
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u8 unknown; //?, looks unused
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u8 num_hunks; //0x20 = 1 hunk, other values not supported
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u8 size; //total size of all hunk#_code[] in bytes
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u8 hunk1_when; //mark when hunk1_code gets executed
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u8 hunk1_size; //sizeof(hunk1_code)
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u16 padding; //0x0000, hunk2 is not supported
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u32 hunk1_code[PWRDN_LENGTH]; //commands, see below
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} powerdown;
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} selfboot_patch = {
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/* Keep the following invariant for valid Selfboot patches */
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.header.signature = 0xA5,
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.header.format = 0x23, //format 1 revision 3
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.header.unknown1 = { 0x61, 0xB1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
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.header.checksum = 0, //calculated later
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.header.unknown2 = 0x30,
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.init.checksum = 0, //calculated later
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.init.unknown = 0x00,
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.init.num_hunks = sizeof(selfboot_patch.init.hunk4_code) ? 0x80 : 0x60,
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.init.size = sizeof(selfboot_patch.init.hunk1_code)
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+ sizeof(selfboot_patch.init.hunk2_code)
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+ sizeof(selfboot_patch.init.hunk3_code)
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+ sizeof(selfboot_patch.init.hunk4_code),
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.init.hunk1_size = sizeof(selfboot_patch.init.hunk1_code),
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.init.hunk2_size = sizeof(selfboot_patch.init.hunk2_code),
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.init.hunk3_size = sizeof(selfboot_patch.init.hunk3_code),
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.init.hunk4_size = sizeof(selfboot_patch.init.hunk4_code),
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.powerdown.checksum = 0, //calculated later
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.powerdown.unknown = 0x00,
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.powerdown.num_hunks = 0x20,
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.powerdown.size = sizeof(selfboot_patch.powerdown.hunk1_code),
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.powerdown.hunk1_size = sizeof(selfboot_patch.powerdown.hunk1_code),
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.powerdown.padding = be16(0x0000),
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/* Only the lines below may be adapted to your needs ... */
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#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF)
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.header.mac_addr = { 0x00, 0x10, 0x18, 0x00, 0x00, 0x00 }, //Broadcom
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.header.subsys_device = be16(0x1699), //same as pci_device
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.header.subsys_vendor = be16(0x14E4), //Broadcom
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#else
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.header.mac_addr = { 0x00, 0x20, 0x9D, 0x00, 0x00, 0x00 }, //LiPPERT
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.header.subsys_device = be16(0x1699), //simply kept this
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.header.subsys_vendor = be16(0x121D), //LiPPERT
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#endif
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.header.pci_device = be16(0x1699), //Broadcom 5785 with GbE PHY
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#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF)
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.header.patch_version = be16(0x010B), //1.11 (Broadcom's sb5785m1.11)
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#else
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.header.patch_version = be16(0x110B), //1.11b, i.e. hacked :-)
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#endif
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/* Bitfield enabling general features/codepaths in the firmware or
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* selecting support for one of several supported PHYs?
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* Bits not listed had no appearent effect:
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* 14-11: any bit 1 = firmware execution seemed delayed
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* 10: 0 = firmware execution seemed delayed
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* 9,2,0: select PHY type, affects these registers, probably more
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* 9 2 0 | reg 0x05A4 PHY reg 31 PHY 23,24,28 Notes
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* -------+----------------------------------------------------------
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* 0 0 0 | 0x331C71C1 - changed Inband Status enabled
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* 0 1 0 | 0x3210C500 - changed -
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* 0 X 1 | 0x33FF66C0 changed - 10/100 Mbit only
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* 1 X 0 | 0x330C5180 - - -
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* 1 X 1 | 0x391C6140 - - -
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*/
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#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF)
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.header.basic_config = be16(0x0404), //original for B50610
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#else
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.header.basic_config = be16(0x0604), //bit 9 set so not to mess up PHY regs, kept other bits unchanged
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#endif
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/* Tag that defines when / on what occasion the commands are interpreted.
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* Bits 2-0 = 0 i.e. possible values are 0x00, 08, 10, ..., F8.
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* On a RISC CPU reset every tag except 0x38, A0, F0, F8 is used. 0x38
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* seems to be run before a reset is performed(?), the other 3 I have
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* never seen used. Generally, lower values appear to be run earlier.
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* An "ifconfig up" with Linux' "tg3" driver causes the tags 0x50, 60,
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* 68, 20, 70, 80 to be interpreted in this order.
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* All tests were performed with .basic_config = 0x0604.
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*/
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.init.hunk1_when = 0x10, //only once at RISC CPU reset?
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/* Instructions are obviously a specialized bytecode interpreted by the
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* main firmware, rather than MIPS machine code. Commands consist of 1-3
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* 32-bit words. In the following, 0-9,A-F = hex literals, a-z,_ = variable
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* parts, each character = 4 bits.
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* 0610offs newvalue: write (32-bit) <newvalue> to 5785-internal shared mem at <offs>
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* 08rgvalu: write <valu> to PHY register, <rg> = 0x20 + register number
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* C610rgnr newvalue: write <newvalue> to MAC register <rgnr>
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* C1F0rgnr andvalue or_value: modify MAC register <rgnr> by ANDing with <andvalue> and then ORing with <or_value>
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* C4btrgnr: clear bit in 32-bit MAC register <rgnr>, <bt> = bit number << 3
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* C3btrgnr: set bit, see C4...; example: command 0xC3200454 sets bit 4 of 32-bit register 0x0454
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* CBbtrgnr: run next command only if bit (see C4...) == 1 (so far only seen before F7F0...)
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* F7F0skip: unconditional jump i.e. skip next <skip> code bytes (only seen small positive <skip>)
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* F7Fxaddr: call function at <addr> in main firmware? <x> = 3 or 4, bool parameter?? Wild guess!
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* F7FFFadr somvalue: also call func. at <adr>, but with <somvalue> as parameter?? More guessing!
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* More commands probably exist, but all code I've ever seen was kept
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* included below, commented out if not suitable for the CFR-AF. v1.xx
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* is Broadcom's Selfboot patch version sb5785m1.xx where the command
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* was added, for reference see Broadcom's changelog.
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*/
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.init.hunk1_code = {
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#if IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF)
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be(0x082B8104), //CFR-AF: PHY0B: KSZ9021 select PHY104
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be(0x082CF0F0), //CFR-AF: PHY0C: KSZ9021 clk/ctl skew (advised by Micrel)
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be(0x082B8105), //CFR-AF: PHY0B: KSZ9021 select PHY105
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be(0x082C3333), //CFR-AF: PHY0C: KSZ9021 RX data skew (empirical)
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#endif
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be(0xC1F005A0), be(0xFEFFEFFF), be(0x01001000), //v1.05 : 5A0.24,12 = 1: auto-clock-switch
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be(0x06100D34), be(0x00000000), //v1.03 : MemD34: clear config vars
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be(0x06100D38), be(0x00000000), //v1.03 : - |
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be(0x06100D3C), be(0x00000000), //v1.03 : MemD3F|
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}, //-->INIT1_LENGTH!
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.init.hunk2_when = 0x30, //after global reset, PHY reset
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.init.hunk2_code = {
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#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF)
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be(0x08370F08), //v1.06 : PHY17: B50610 select reg. 08
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be(0x08350001), //v1.06 : PHY15: B50610 slow link fix
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be(0x08370F00), //v1.06 : PHY17: B50610 disable reg. 08
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be(0x083C2C00), //v1.11 : PHY1C: B50610 Shadow 0B
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#endif
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be(0xF7F301E6), //v1.09+: ?: subroutine calls to
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be(0xF7FFF0B6), be(0x0000FFE7), //v1.09+: ?| restore Port Mode ???
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be(0xF7FFF0F6), be(0x00008000), //v1.09+: ?|
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be(0xF7F401E6), //v1.09+: ?|
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}, //-->INIT2_LENGTH!
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.init.hunk3_when = 0xA8, //?, I'd guess quite late
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.init.hunk3_code = {
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be(0xC1F03604), be(0xFFE0FFFF), be(0x00110000), //v1.08 : 3604.20-16: 10Mb clock = 12.5MHz
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}, //-->INIT3_LENGTH!
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#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF)
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.init.hunk4_when = 0xD8, //original for B50610
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#else
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.init.hunk4_when = 0x80, //run last, after Linux' "ifconfig up"
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#endif
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.init.hunk4_code = {
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#if IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF)
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be(0x083F4300), //CFR-AF: PHY1F: IRQ active high
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be(0x083C0000), //CFR-AF: PHY1C: revert driver writes
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be(0x08380000), //CFR-AF: PHY18|
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be(0x083C0000), //CFR-AF: PHY1C|
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#endif
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be(0xCB0005A4), be(0xF7F0000C), //v1.01 : if 5A4.0 == 1 -->skip next 12 bytes
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#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF)
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be(0xC61005A4), be(0x3210C500), //v1.01 : 5A4: PHY LED mode
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#else
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be(0xC61005A4), be(0x331C71CE), //CFR-AF: 5A4: fake LED mode
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#endif
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be(0xF7F00008), //v1.01 : -->skip next 8 bytes
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be(0xC61005A4), be(0x331C71C1), //v1.01 : 5A4: inband LED mode
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//be(0xC3200454), //CFR-AF: 454.4: auto link polling
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}, //-->INIT4_LENGTH!
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.powerdown.hunk1_when = 0x50, //prior to IDDQ MAC
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.powerdown.hunk1_code = {
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#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF)
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be(0x083CB001), //v1.10 : PHY1C: IDDQ B50610 PHY
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#endif
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be(0xF7F30116), // IDDQ PHY
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be(0xC40005A0), //v1.09 : 5A0.0 = 0: Port Mode = MII
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be(0xC4180400), //v1.09 : 400.3 = 0|
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be(0xC3100400), //v1.09 : 400.2 = 1|
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}, //-->PWRDN_LENGTH!
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};
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/* Upload 'NV'RAM contents for BCM5785 GbE MAC integrated in A55E.
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* Call this from mainboard.c.
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*/
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void broadcom_init(void)
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{
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volatile u32 *gec_base; //Gigabit Ethernet Controller base addr
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u8 *gec_shadow; //base addr of shadow 'NV'RAM for GbE MAC in A55E
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u8 sum;
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int i;
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||||
gec_base = (u32*)(uintptr_t)dev_find_slot(0, PCI_DEVFN(0x14, 6))->resource_list->base;
|
||||
gec_shadow = (u8*)((uintptr_t)pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x14, 3)), 0x9C) & 0xFFFFFC00);
|
||||
printk(BIOS_DEBUG, "Upload GbE 'NV'RAM contents @ 0x%08lx\n", (unsigned long)gec_shadow);
|
||||
|
||||
/* Halt RISC CPU before uploading the firmware patch */
|
||||
for (i = 10000; i > 0; i--) {
|
||||
gec_base[0x5004/4] = 0xFFFFFFFF; //clear CPU state
|
||||
gec_base[0x5000/4] |= (1 << 10); //issue RISC halt
|
||||
if (gec_base[0x5000/4] | (1 << 10))
|
||||
break;
|
||||
udelay(10);
|
||||
}
|
||||
if (!i)
|
||||
printk(BIOS_ERR, "Failed to halt RISC CPU!\n");
|
||||
|
||||
/* Calculate checksums (standard byte sum) */
|
||||
for (sum = 0, i = 0; i < sizeof(selfboot_patch.header); i++)
|
||||
sum -= ((u8*)&selfboot_patch.header)[i];
|
||||
selfboot_patch.header.checksum = sum;
|
||||
for (sum = 0, i = 0; i < sizeof(selfboot_patch.init); i++)
|
||||
sum -= ((u8*)&selfboot_patch.init)[i];
|
||||
selfboot_patch.init.checksum = sum;
|
||||
for (sum = 0, i = 0; i < sizeof(selfboot_patch.powerdown); i++)
|
||||
sum -= ((u8*)&selfboot_patch.powerdown)[i];
|
||||
selfboot_patch.powerdown.checksum = sum;
|
||||
|
||||
/* Upload firmware patch to shadow 'NV'RAM */
|
||||
for (i = 0; i < sizeof(selfboot_patch); i++)
|
||||
gec_shadow[i] = ((u8*)&selfboot_patch)[i]; //access byte-wise!
|
||||
|
||||
/* Restart BCM5785's CPU */
|
||||
gec_base[0x5004/4] = 0xFFFFFFFF; //clear CPU state
|
||||
gec_base[0x5000/4] = 0x00000001; //reset RISC processor
|
||||
//usually we'd have to wait for the reset bit to clear again ...
|
||||
}
|
||||
|
|
@ -19,8 +19,6 @@
|
|||
#include <southbridge/amd/sb800/sb800.h>
|
||||
#include "SBPLATFORM.h" /* Platfrom Specific Definitions */
|
||||
|
||||
void broadcom_init(void);
|
||||
|
||||
static void init_gpios(void)
|
||||
{
|
||||
/**
|
||||
|
|
@ -68,10 +66,6 @@ static void mainboard_enable(device_t dev)
|
|||
*/
|
||||
pm_iowrite(0x29, 0x80);
|
||||
pm_iowrite(0x28, 0x61);
|
||||
|
||||
/* Upload AMD A55E GbE 'NV'RAM contents. Still untested on Inagua.
|
||||
* After anyone can confirm it works please uncomment the call. */
|
||||
//broadcom_init();
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
|
|
|
|||
Loading…
Reference in New Issue