Use existing, readable MTRR #defines instead of hardcoding numbers.
Replace $0x200 with $MTRRphysBase_MSR(0) etc. Also, move some #ifdef stuff a little bit around (should not affect any functionality) to make the Intel/AMD/VIA CAR implementations more similar and easier to compare. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5887 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
parent
8463dd9db0
commit
1d36d6df7d
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@ -243,13 +243,13 @@ clear_fixed_var_mtrr_out:
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#if CacheSize > 0x8000
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/* enable caching for 32K-64K using fixed mtrr */
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movl $0x268, %ecx /* fix4k_c0000*/
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movl $MTRRfix4K_C0000_MSR, %ecx
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simplemask CacheSize, 0x8000
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wrmsr
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#endif
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/* enable caching for 0-32K using fixed mtrr */
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movl $0x269, %ecx /* fix4k_c8000*/
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movl $MTRRfix4K_C8000_MSR, %ecx
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simplemask CacheSize, 0
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wrmsr
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@ -260,22 +260,23 @@ clear_fixed_var_mtrr_out:
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wrmsr
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#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
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/* enable write base caching so we can do execute in place
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* on the flash rom.
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*/
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movl $0x202, %ecx
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xorl %edx, %edx
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#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
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#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
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#else
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#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
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#endif
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/* enable write base caching so we can do execute in place
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* on the flash rom.
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*/
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movl $MTRRphysBase_MSR(1), %ecx
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xorl %edx, %edx
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movl $REAL_XIP_ROM_BASE, %eax
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orl $MTRR_TYPE_WRBACK, %eax
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wrmsr
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movl $0x203, %ecx
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movl $MTRRphysMask_MSR(1), %ecx
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movl $0xff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for K8 (CONFIG_CPU_ADDR_BITS = 40) */
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jmp_if_k8(wbcache_post_fam10_setup)
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movl $0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */
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@ -196,11 +196,13 @@ clear_fixed_var_mtrr_out:
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wrmsr
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#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
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#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
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#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
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#else
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#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
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#endif
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/* enable write base caching so we can do execute in place
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* on the flash rom.
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*/
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@ -78,36 +78,33 @@ var_mtrr_msr:
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.long 0x000 /* NULL, end of table */
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clear_fixed_var_mtrr_out:
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/* MTRRPhysBase */
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movl $0x200, %ecx
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movl $MTRRphysBase_MSR(0), %ecx
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xorl %edx, %edx
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movl $(CacheBase|MTRR_TYPE_WRBACK),%eax
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wrmsr
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/* MTRRPhysMask */
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movl $0x201, %ecx
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movl $MTRRphysMask_MSR(0), %ecx
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/* This assumes we never access addresses above 2^36 in CAR. */
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movl $0x0000000f,%edx
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movl $(~(CacheSize-1)|0x800),%eax
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wrmsr
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/* enable write base caching so we can do execute in place
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* on the flash rom.
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*/
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/* MTRRPhysBase */
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movl $0x202, %ecx
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xorl %edx, %edx
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#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
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#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
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#else
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#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
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#endif
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/* enable write base caching so we can do execute in place
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* on the flash rom.
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*/
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movl $MTRRphysBase_MSR(1), %ecx
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xorl %edx, %edx
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movl $REAL_XIP_ROM_BASE, %eax
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orl $MTRR_TYPE_WRBACK, %eax
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wrmsr
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/* MTRRPhysMask */
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movl $0x203, %ecx
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movl $MTRRphysMask_MSR(1), %ecx
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movl $0x0000000f, %edx
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movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
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wrmsr
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@ -195,8 +192,7 @@ testok:
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/* Set the default memory type and disable fixed and enable variable MTRRs */
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movl $0x2ff, %ecx
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//movl $MTRRdefType_MSR, %ecx
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movl $MTRRdefType_MSR, %ecx
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xorl %edx, %edx
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/* Enable Variable and Disable Fixed MTRRs */
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@ -204,7 +200,7 @@ testok:
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wrmsr
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/* enable caching for first 1M using variable mtrr */
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movl $0x200, %ecx
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movl $MTRRphysBase_MSR(0), %ecx
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xorl %edx, %edx
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movl $(0 | 6), %eax
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//movl $(0 | MTRR_TYPE_WRBACK), %eax
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@ -216,41 +212,41 @@ testok:
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* And in x86_setup_fixed_mtrrs()(mtrr.c), 0-256M is set cacheable.
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*/
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movl $0x201, %ecx
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movl $MTRRphysMask_MSR(0), %ecx
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movl $0x0000000f, %edx /* AMD 40 bit 0xff*/
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movl $((~(( 0 + 0x80000) - 1)) | 0x800), %eax
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wrmsr
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movl $0x202, %ecx
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movl $MTRRphysBase_MSR(1), %ecx
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xorl %edx, %edx
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movl $(0x80000 | 6), %eax
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orl $(0 | 6), %eax
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wrmsr
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movl $0x203, %ecx
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movl $MTRRphysMask_MSR(1), %ecx
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movl $0x0000000f, %edx /* AMD 40 bit 0xff*/
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movl $((~(( 0 + 0x20000) - 1)) | 0x800), %eax
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wrmsr
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movl $0x204, %ecx
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movl $MTRRphysBase_MSR(2), %ecx
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xorl %edx, %edx
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movl $(0xc0000 | 6), %eax
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orl $(0 | 6), %eax
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wrmsr
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movl $0x205, %ecx
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movl $MTRRphysMask_MSR(2), %ecx
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movl $0x0000000f, %edx /* AMD 40 bit 0xff*/
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movl $((~(( 0 + 0x40000) - 1)) | 0x800), %eax
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wrmsr
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/* cache XIP_ROM_BASE-SIZE to speedup coreboot code */
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movl $0x206, %ecx
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movl $MTRRphysBase_MSR(3), %ecx
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xorl %edx, %edx
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movl $REAL_XIP_ROM_BASE,%eax
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orl $(0 | 6), %eax
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wrmsr
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movl $0x207, %ecx
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movl $MTRRphysMask_MSR(3), %ecx
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xorl %edx, %edx
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movl $CONFIG_XIP_ROM_SIZE,%eax
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decl %eax
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