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mb/google/hatch/var/scout: improve USB2 port 4 strength 

Set USB2 port 4 pre emphasis to 15mV for passing USB2 port 4 SI (margin eye diagram).

BUG=b:210755120
TEST=emerge-ambassadorcoreboot chromeos-bootimage; Build local fw and pass to HW for measuring USB2 port 4 eye diagram.

Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: I8163b2be6c9094eaf08efc0325cf211235556dc8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kenneth Chan 2021-12-15 14:05:40 +08:00 committed by Felix Held
parent 520a4a618f
commit 1d3cff3f61
1 changed files with 8 additions and 1 deletions
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9
src/mainboard/google/hatch/variants/scout/overridetree.cb
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@ -42,7 +42,14 @@ chip soc/intel/cannonlake
.pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bias = USB2_BIAS_28P15MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Type-A Port 3 }" # Type-A Port 3
register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port register "usb2_ports[3]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_28P15MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Type-C Port
register "usb2_ports[4]" = "{ register "usb2_ports[4]" = "{
.enable = 1, .enable = 1,
.ocpin = OC_SKIP, .ocpin = OC_SKIP,