From 1d3e6eba02b074cf02615037694563db8854d3f1 Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Mon, 31 Jul 2023 14:15:27 -0600 Subject: [PATCH] mb/system76: Enable C10 reporting on systems using eSPI Report CPU C10 state over eSPI so that the EC can use Virtual Wires to detect if PECI can be used. Change-Id: I301361f35caee8ba1c3fd9227219603897add92b Signed-off-by: Tim Crawford Reviewed-on: https://review.coreboot.org/c/coreboot/+/76910 Reviewed-by: Jeremy Soller Tested-by: build bot (Jenkins) --- src/mainboard/system76/adl/ramstage.c | 3 +++ src/mainboard/system76/tgl-h/variants/gaze16-3050/ramstage.c | 3 +++ src/mainboard/system76/tgl-h/variants/gaze16-3060/ramstage.c | 3 +++ src/mainboard/system76/tgl-h/variants/oryp8/ramstage.c | 3 +++ 4 files changed, 12 insertions(+) diff --git a/src/mainboard/system76/adl/ramstage.c b/src/mainboard/system76/adl/ramstage.c index c767f2dfe6..aa9a1b76a7 100644 --- a/src/mainboard/system76/adl/ramstage.c +++ b/src/mainboard/system76/adl/ramstage.c @@ -17,6 +17,9 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) params->SataPortDevSlpPinMux[1] = 0x5967400d; // GPP_H13 params->SataPortsSolidStateDrive[1] = 1; + + // Enable reporting CPU C10 state over eSPI + params->PchEspiHostC10ReportEnable = 1; } static void mainboard_init(void *chip_info) diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/ramstage.c b/src/mainboard/system76/tgl-h/variants/gaze16-3050/ramstage.c index 9d985630d0..0d4ae48dc1 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3050/ramstage.c +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/ramstage.c @@ -18,4 +18,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) // Remap PEG2 as PEG1 params->CpuPcieRpFunctionSwap = 1; + + // Enable reporting CPU C10 state over eSPI + params->PchEspiHostC10ReportEnable = 1; } diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/ramstage.c b/src/mainboard/system76/tgl-h/variants/gaze16-3060/ramstage.c index 0f83461ae4..93808a1472 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3060/ramstage.c +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/ramstage.c @@ -15,4 +15,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) params->CpuPcieRpAdvancedErrorReporting[1] = 0; params->CpuPcieRpLtrEnable[1] = 1; params->CpuPcieRpPtmEnabled[1] = 0; + + // Enable reporting CPU C10 state over eSPI + params->PchEspiHostC10ReportEnable = 1; } diff --git a/src/mainboard/system76/tgl-h/variants/oryp8/ramstage.c b/src/mainboard/system76/tgl-h/variants/oryp8/ramstage.c index 72ad3fc5e7..bb50326188 100644 --- a/src/mainboard/system76/tgl-h/variants/oryp8/ramstage.c +++ b/src/mainboard/system76/tgl-h/variants/oryp8/ramstage.c @@ -21,4 +21,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) // Low latency legacy I/O params->PchLegacyIoLowLatency = 1; + + // Enable reporting CPU C10 state over eSPI + params->PchEspiHostC10ReportEnable = 1; }