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soc/intel/alderlake: Rename SOC_INTEL_ALDERLAKE_S3 to D3COLD_SUPPORT 

The Kconfig option SOC_INTEL_ALDERLAKE_S3 suggests that it's doing
something with S3, but it's actually disabling D3Cold support.

Rename it to D3COLD_SUPPORT to make it clear what it's doing.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ifc3f19912ac7ee55be8ec7a491598140f9532675
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Sean Rhodes 2023-04-13 12:08:58 +01:00
parent bf66d66593
commit 1d41f909f3
8 changed files with 36 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/prodrive/atlas/Kconfig
View File

@ -11,7 +11,6 @@ config BOARD_PRODRIVE_ATLAS_BASEBOARD
select MEMORY_MAPPED_TPM
select PCIEXP_SUPPORT_RESIZABLE_BARS
select SOC_INTEL_ALDERLAKE_PCH_P
select SOC_INTEL_ALDERLAKE_S3
if BOARD_PRODRIVE_ATLAS_BASEBOARD
@ -26,6 +25,9 @@ config ATLAS_ENABLE_IBECC
and therefore not always required.
default n
config D3COLD_SUPPORT
default n
config MAINBOARD_FAMILY
string
default "PRODRIVE_ATLAS_SERIES"

4
src/mainboard/starlabs/starbook/Kconfig
View File

@ -62,7 +62,6 @@ config BOARD_STARLABS_STARBOOK_ADL
select MEMORY_MAPPED_TPM
select SOC_INTEL_ALDERLAKE
select SOC_INTEL_ALDERLAKE_PCH_P
select SOC_INTEL_ALDERLAKE_S3
select SPI_FLASH_WINBOND
select TPM_MEASURED_BOOT
select PCIEXP_SUPPORT_RESIZABLE_BARS
@ -84,6 +83,9 @@ config CMOS_LAYOUT_FILE
config CONSOLE_SERIAL
default n if !EDK2_DEBUG
config D3COLD_SUPPORT
default n
config DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"

14
src/soc/intel/alderlake/Kconfig
View File

@ -332,11 +332,19 @@ config SOC_INTEL_I2C_DEV_MAX
int
default 8
config SOC_INTEL_ALDERLAKE_S3
config D3COLD_SUPPORT
bool
default n
default y
help
Select if using S3 instead of S0ix to disable D3Cold.
Enable this option if all devices on your system support the
D3Cold power management state. The D3Cold state is a low-power
state where the device has been powered down and is no longer
able to maintain its context. This state can help reduce
overall system power consumption, which can be beneficial for
energy savings and thermal management.
Please note that enabling D3Cold support may break system
suspend-to-RAM (S3) functionality.
config ENABLE_SATA_TEST_MODE
bool "Enable test mode for SATA margining"

4
src/soc/intel/alderlake/acpi/tcss.asl
View File

@ -583,7 +583,7 @@ Scope (\_SB.PCI0)
}
}
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
#if CONFIG(D3COLD_SUPPORT)
Method (TCON, 0)
{
/* Reset IOM D3 cold bit if it is in D3 cold now. */
@ -654,7 +654,7 @@ Scope (\_SB.PCI0)
STAT = 0
}
}
#endif // SOC_INTEL_ALDERLAKE_S3
#endif // D3COLD_SUPPORT
/*
* TCSS xHCI device

12
src/soc/intel/alderlake/acpi/tcss_dma.asl
View File

@ -28,16 +28,16 @@ Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */
Method (_S0W, 0x0)
{
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
#if CONFIG(D3COLD_SUPPORT)
Return (0x04)
#else
Return (0x03)
#endif // SOC_INTEL_ALDERLAKE_S3
#endif // D3COLD_SUPPORT
}
Method (_PR0)
{
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
#if CONFIG(D3COLD_SUPPORT)
If (DUID == 0) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
@ -49,12 +49,12 @@ Method (_PR0)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
#endif // SOC_INTEL_ALDERLAKE_S3
#endif // D3COLD_SUPPORT
}
Method (_PR3)
{
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
#if CONFIG(D3COLD_SUPPORT)
If (DUID == 0) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
@ -66,7 +66,7 @@ Method (_PR3)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
#endif // SOC_INTEL_ALDERLAKE_S3
#endif // D3COLD_SUPPORT
}
/*

12
src/soc/intel/alderlake/acpi/tcss_pcierp.asl
View File

@ -247,16 +247,16 @@ Method (_PS3, 0, Serialized)
Method (_S0W, 0x0, NotSerialized)
{
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
#if CONFIG(D3COLD_SUPPORT)
Return (0x4)
#else
Return (0x3)
#endif // SOC_INTEL_ALDERLAKE_S3
#endif // D3COLD_SUPPORT
}
Method (_PR0)
{
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
#if CONFIG(D3COLD_SUPPORT)
If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
@ -268,12 +268,12 @@ Method (_PR0)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
#endif // SOC_INTEL_ALDERLAKE_S3
#endif // D3COLD_SUPPORT
}
Method (_PR3)
{
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
#if CONFIG(D3COLD_SUPPORT)
If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
@ -285,7 +285,7 @@ Method (_PR3)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
#endif // SOC_INTEL_ALDERLAKE_S3
#endif // D3COLD_SUPPORT
}
/*

8
src/soc/intel/alderlake/acpi/tcss_xhci.asl
View File

@ -30,11 +30,11 @@ Method (_PS3, 0, Serialized)
Method (_S0W, 0x0, NotSerialized)
{
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
#if CONFIG(D3COLD_SUPPORT)
Return (0x4)
#else
Return (0x3)
#endif // SOC_INTEL_ALDERLAKE_S3
#endif // D3COLD_SUPPORT
}
/*
@ -43,7 +43,7 @@ Method (_S0W, 0x0, NotSerialized)
*/
Name (SD3C, 0)
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
#if CONFIG(D3COLD_SUPPORT)
Method (_PR0)
{
Return (Package () { \_SB.PCI0.D3C })
@ -53,7 +53,7 @@ Method (_PR3)
{
Return (Package () { \_SB.PCI0.D3C })
}
#endif // SOC_INTEL_ALDERLAKE_S3
#endif // D3COLD_SUPPORT
/*
* XHCI controller _DSM method

2
src/soc/intel/alderlake/fsp_params.c
View File

@ -648,7 +648,7 @@ static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg,
/* D3Hot and D3Cold for TCSS */
s_cfg->D3HotEnable = !config->tcss_d3_hot_disable;
s_cfg->D3ColdEnable = !CONFIG(SOC_INTEL_ALDERLAKE_S3) && !config->tcss_d3_cold_disable;
s_cfg->D3ColdEnable = CONFIG(D3COLD_SUPPORT) && !config->tcss_d3_cold_disable;
s_cfg->UsbTcPortEn = 0;
for (int i = 0; i < MAX_TYPE_C_PORTS; i++) {