This patch adds support for K8T890CE northbridge.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2883 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Rudolf Marek
Uwe Hermann
parent
bed2f9c2fe
commit
1d4fc0cff9
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##
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## This file is part of the LinuxBIOS project.
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##
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## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License v2 as published by
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## the Free Software Foundation.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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driver k8t890_ctrl.o
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driver k8t890_dram.o
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driver k8t890_host.o
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driver k8t890_host_ctrl.o
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driver k8t890_pcie.o
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driver k8t890_traf_ctrl.o
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/*
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License v2 as published by
|
||||||
|
* the Free Software Foundation.
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||||||
|
*
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* This program is distributed in the hope that it will be useful,
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||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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|
* GNU General Public License for more details.
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||||||
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*
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||||||
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* You should have received a copy of the GNU General Public License
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||||||
|
* along with this program; if not, write to the Free Software
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||||||
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef SOUTHBRIDGE_VIA_K8T890_K8T890_H
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#define SOUTHBRIDGE_VIA_K8T890_K8T890_H
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/* Static resources for K8T890. */
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#define K8T890_APIC_ID 0x3
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/*
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* Please check the datasheet and traf_ctrl_enable before change!
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* It can't be changed to an arbitrary address.
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*/
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#define K8T890_APIC_BASE 0xfecc0000
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#define K8T890_MMCONFIG_MBAR 0x61
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#define K8T890_MULTIPLE_FN_EN 0x4f
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#endif
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@ -0,0 +1,102 @@
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/*
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License v2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <device/pci_ids.h>
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#include <console/console.h>
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static void ctrl_enable(struct device *dev)
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{
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u8 regm, regm2, regm3;
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device_t devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
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PCI_DEVICE_ID_VIA_K8T890CE_3, 0);
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/* TODO: Fix some ordering issue fo V-link set Rx77[6] and PCI1_Rx4F[0]
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should to 1 */
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/* C2P Read ACK Return Priority */
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/* PCI CFG Address bits[27:24] are used as extended register address
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bit[11:8] */
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pci_write_config8(dev, 0x47, 0x30);
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/* FIXME: Program V-link 8X 16bit full duplex, this needs to be fixed
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for other than VT8237R SB */
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pci_write_config8(dev, 0x48, 0x23);
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/* Magic init. This is not well documented :/ */
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pci_write_config8(dev, 0x70, 0xc2);
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/* PCI Control */
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pci_write_config8(dev, 0x72, 0xee);
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pci_write_config8(dev, 0x73, 0x01);
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pci_write_config8(dev, 0x74, 0x24);
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pci_write_config8(dev, 0x75, 0x0f);
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pci_write_config8(dev, 0x76, 0x50);
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pci_write_config8(dev, 0x77, 0x08);
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pci_write_config8(dev, 0x78, 0x01);
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/* APIC on HT */
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pci_write_config8(dev, 0x7c, 0x7f);
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pci_write_config8(dev, 0x7f, 0x02);
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/* WARNING: Need to copy some registers from NB (D0F3) to SB (D0F7). */
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regm = pci_read_config8(devfun3, 0x88); /* Shadow mem CTRL */
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pci_write_config8(dev, 0x57, regm);
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regm = pci_read_config8(devfun3, 0x80); /* Shadow page C */
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pci_write_config8(dev, 0x61, regm);
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regm = pci_read_config8(devfun3, 0x81); /* Shadow page D */
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pci_write_config8(dev, 0x62, regm);
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regm = pci_read_config8(devfun3, 0x86); /* SMM and APIC decoding */
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pci_write_config8(dev, 0xe6, regm);
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regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */
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/*
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* All access bits for 0xE0000-0xEFFFF encode as just 2 bits!
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* So the NB reg is quite inconsistent, we expect there only 0xff or 0x00,
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* and write them to 0x63 7-6 but! VIA 8237A has the mirror at 0x64!
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*/
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if (regm3 == 0xff)
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regm3 = 0xc0;
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else
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regm3 = 0x0;
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/* Shadow page F + memhole copy */
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regm = pci_read_config8(devfun3, 0x83);
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pci_write_config8(dev, 0x63, regm3 | (regm & 0x3F));
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}
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static struct device_operations ctrl_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.enable = ctrl_enable,
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.ops_pci = 0,
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};
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static struct pci_driver northbridge_driver __pci_driver = {
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.ops = &ctrl_ops,
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.vendor = PCI_VENDOR_ID_VIA,
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.device = PCI_DEVICE_ID_VIA_K8T890CE_7,
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};
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@ -0,0 +1,78 @@
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/*
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License v2 as published by
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|
* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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||||||
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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||||||
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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||||||
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*
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* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <device/pci_ids.h>
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#include <console/console.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/mtrr.h>
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static void dram_enable(struct device *dev)
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{
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msr_t msr;
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u16 reg;
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/*
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* Enable Lowest Interrupt arbitration for APIC, enable NB APIC
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* decoding, MSI support, no SMRAM, compatible SMM.
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*/
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pci_write_config8(dev, 0x86, 0x39);
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/*
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* We want to use the 0xC0000-0xEFFFF as RAM mark area as RW, even if
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* memory is doing K8 the DMA from SB will fail if we have it wrong,
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* AND even we have it here, we must later copy it to SB to make it work :/
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*/
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/* For CC000-CFFFF, bits 7:6 (10 = REn, 01 = WEn) bits 1:0 for
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* C0000-C3FFF etc.
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*/
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pci_write_config8(dev, 0x80, 0xff);
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/* For page D0000-DFFFF */
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pci_write_config8(dev, 0x81, 0xff);
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/* For page E0000-EFFFF */
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pci_write_config8(dev, 0x82, 0xff);
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pci_write_config8(dev, 0x83, 0x30);
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msr = rdmsr(TOP_MEM);
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reg = pci_read_config16(dev, 0x84);
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reg &= 0xf;
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pci_write_config16(dev, 0x84, (msr.lo >> 16) | reg);
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reg = pci_read_config16(dev, 0x88);
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reg &= 0xf800;
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pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg);
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}
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static struct device_operations dram_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.enable = dram_enable,
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.ops_pci = 0,
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};
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static struct pci_driver northbridge_driver __pci_driver = {
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.ops = &dram_ops,
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.vendor = PCI_VENDOR_ID_VIA,
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.device = PCI_DEVICE_ID_VIA_K8T890CE_3,
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};
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/*
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License v2 as published by
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|
* the Free Software Foundation.
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|
*
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* This program is distributed in the hope that it will be useful,
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|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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|
* GNU General Public License for more details.
|
||||||
|
*
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|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
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|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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* Seems the link and width of HT link needs to be setup too, you need to
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* generate PCI reset or LDTSTOP to apply.
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*/
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u8 k8t890_early_setup_car(u8 width, u8 speed)
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{
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u8 awidth, aspeed;
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print_debug("LDT width and speed for K8T890 was");
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awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x67);
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print_debug_hex8(awidth);
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aspeed = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x6d);
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print_debug_hex8(aspeed);
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if ((aspeed == speed) && (((width == 16) && (awidth == 0x11)) ||
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((width == 8) && (awidth == 0x00))))
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return 0;
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/* Update the desired HT LNK capabilities in NB too. */
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pci_write_config8(PCI_DEV(0, 0x0, 0), 0x67,
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(width == 16) ? 0x11 : 0x00);
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pci_write_config8(PCI_DEV(0, 0x0, 0), 0x6d, speed);
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print_debug(" and will after HT reset: ");
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awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x67);
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print_debug_hex8(awidth);
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aspeed = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x6d);
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print_debug_hex8(aspeed);
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print_debug("\n");
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return 1;
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}
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@ -0,0 +1,45 @@
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/*
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
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*
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* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License v2 as published by
|
||||||
|
* the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <device/pci_ids.h>
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#include <console/console.h>
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#include "k8t890.h"
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static void host_enable(struct device *dev)
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{
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/* Multiple function control */
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pci_write_config8(dev, K8T890_MULTIPLE_FN_EN, 0x01);
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}
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static struct device_operations host_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.enable = host_enable,
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.ops_pci = 0,
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};
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static struct pci_driver northbridge_driver __pci_driver = {
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.ops = &host_ops,
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.vendor = PCI_VENDOR_ID_VIA,
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.device = PCI_DEVICE_ID_VIA_K8T890CE_0,
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};
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@ -0,0 +1,93 @@
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/*
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* This file is part of the LinuxBIOS project.
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||||||
|
*
|
||||||
|
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License v2 as published by
|
||||||
|
* the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <device/device.h>
|
||||||
|
#include <device/pci.h>
|
||||||
|
#include <device/pci_ops.h>
|
||||||
|
#include <device/pci_ids.h>
|
||||||
|
#include <console/console.h>
|
||||||
|
|
||||||
|
/* This fine tunes the HT link settings, which were loaded by ROM strap. */
|
||||||
|
static void host_ctrl_enable(struct device *dev)
|
||||||
|
{
|
||||||
|
dump_south(dev);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Bit 4 is reserved but set by AW. Set PCI to HT outstanding
|
||||||
|
* requests to 3.
|
||||||
|
*/
|
||||||
|
pci_write_config8(dev, 0xa0, 0x13);
|
||||||
|
|
||||||
|
/* Disable NVRAM and enable non-posted PCI writes. */
|
||||||
|
pci_write_config8(dev, 0xa1, 0x8e);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* NVRAM I/O base 0xe00-0xeff, but it is disabled.
|
||||||
|
* Some bits are set and reserved.
|
||||||
|
*/
|
||||||
|
pci_write_config8(dev, 0xa2, 0x0e);
|
||||||
|
/* Arbitration control, some bits are reserved. */
|
||||||
|
pci_write_config8(dev, 0xa5, 0x3c);
|
||||||
|
|
||||||
|
/* Arbitration control 2 */
|
||||||
|
pci_write_config8(dev, 0xa6, 0x80);
|
||||||
|
|
||||||
|
writeback(dev, 0xa0, 0x13); /* Bit4 is reserved! */
|
||||||
|
writeback(dev, 0xa1, 0x8e); /* Some bits are reserved. */
|
||||||
|
writeback(dev, 0xa2, 0x0e); /* I/O NVRAM base 0xe00-0xeff disabled. */
|
||||||
|
writeback(dev, 0xa3, 0x31);
|
||||||
|
writeback(dev, 0xa4, 0x30);
|
||||||
|
|
||||||
|
writeback(dev, 0xa5, 0x3c); /* Some bits reserved. */
|
||||||
|
writeback(dev, 0xa6, 0x80); /* Some bits reserved. */
|
||||||
|
writeback(dev, 0xa7, 0x86); /* Some bits reserved. */
|
||||||
|
writeback(dev, 0xa8, 0x7f); /* Some bits reserved. */
|
||||||
|
writeback(dev, 0xa9, 0xcf); /* Some bits reserved. */
|
||||||
|
writeback(dev, 0xaa, 0x44);
|
||||||
|
writeback(dev, 0xab, 0x22);
|
||||||
|
writeback(dev, 0xac, 0x35); /* Maybe bit0 is read-only? */
|
||||||
|
|
||||||
|
writeback(dev, 0xae, 0x22);
|
||||||
|
writeback(dev, 0xaf, 0x40);
|
||||||
|
/* b0 is missing. */
|
||||||
|
writeback(dev, 0xb1, 0x13);
|
||||||
|
writeback(dev, 0xb4, 0x02); /* Some bits are reserved. */
|
||||||
|
writeback(dev, 0xc0, 0x20);
|
||||||
|
writeback(dev, 0xc1, 0xaa);
|
||||||
|
writeback(dev, 0xc2, 0xaa);
|
||||||
|
writeback(dev, 0xc3, 0x02);
|
||||||
|
writeback(dev, 0xc4, 0x50);
|
||||||
|
writeback(dev, 0xc5, 0x50);
|
||||||
|
|
||||||
|
dump_south(dev);
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct device_operations host_ctrl_ops = {
|
||||||
|
.read_resources = pci_dev_read_resources,
|
||||||
|
.set_resources = pci_dev_set_resources,
|
||||||
|
.enable_resources = pci_dev_enable_resources,
|
||||||
|
.enable = host_ctrl_enable,
|
||||||
|
.ops_pci = 0,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct pci_driver northbridge_driver __pci_driver = {
|
||||||
|
.ops = &host_ctrl_ops,
|
||||||
|
.vendor = PCI_VENDOR_ID_VIA,
|
||||||
|
.device = PCI_DEVICE_ID_VIA_K8T890CE_2,
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,164 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the LinuxBIOS project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License v2 as published by
|
||||||
|
* the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <console/console.h>
|
||||||
|
#include <device/device.h>
|
||||||
|
#include <device/pci.h>
|
||||||
|
#include <device/pciexp.h>
|
||||||
|
#include <device/pci_ops.h>
|
||||||
|
#include <device/pci_ids.h>
|
||||||
|
|
||||||
|
void peg_init(struct device *dev)
|
||||||
|
{
|
||||||
|
u8 reg;
|
||||||
|
|
||||||
|
printk_debug("Configuring PCIe PEG\n");
|
||||||
|
dump_south(dev);
|
||||||
|
|
||||||
|
/* Disable link. */
|
||||||
|
reg = pci_read_config8(dev, 0x50);
|
||||||
|
pci_write_config8(dev, 0x50, reg | 0x10);
|
||||||
|
|
||||||
|
/* Award has 0xb, VIA recomends 0x4. */
|
||||||
|
pci_write_config8(dev, 0xe1, 0xb);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* pci_write_config8(dev, 0xe2, 0x0);
|
||||||
|
* pci_write_config8(dev, 0xe3, 0x92);
|
||||||
|
*/
|
||||||
|
/* Disable scrambling bit 6 to 1. */
|
||||||
|
pci_write_config8(dev, 0xc0, 0x43);
|
||||||
|
|
||||||
|
/* Set replay timer limit. */
|
||||||
|
pci_write_config8(dev, 0xb1, 0xf0);
|
||||||
|
|
||||||
|
/* Bit0 = 1 SDP (Start DLLP) always at Lane0. */
|
||||||
|
reg = pci_read_config8(dev, 0xb8);
|
||||||
|
pci_write_config8(dev, 0xb8, reg | 0x1);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Downstream wait and Upstream Checking Malformed TLP through
|
||||||
|
* "Byte Enable Rule" And "Over 4K Boundary Rule".
|
||||||
|
*/
|
||||||
|
reg = pci_read_config8(dev, 0xa4);
|
||||||
|
pci_write_config8(dev, 0xa4, reg | 0x30);
|
||||||
|
|
||||||
|
/* Enable link. */
|
||||||
|
reg = pci_read_config8(dev, 0x50);
|
||||||
|
pci_write_config8(dev, 0x50, reg & ~0x10);
|
||||||
|
|
||||||
|
/* Retrain link. */
|
||||||
|
reg = pci_read_config8(dev, 0x50);
|
||||||
|
pci_write_config8(dev, 0x50, reg | 0x20);
|
||||||
|
|
||||||
|
reg = pci_read_config8(dev, 0x3e);
|
||||||
|
reg |= 0x40; /* Bus reset. */
|
||||||
|
pci_write_config8(dev, 0x3e, reg);
|
||||||
|
|
||||||
|
reg = pci_read_config8(dev, 0x3e);
|
||||||
|
reg &= ~0x40; /* Clear reset. */
|
||||||
|
pci_write_config8(dev, 0x3e, reg);
|
||||||
|
|
||||||
|
dump_south(dev);
|
||||||
|
}
|
||||||
|
|
||||||
|
void pcie_init(struct device *dev)
|
||||||
|
{
|
||||||
|
u8 reg;
|
||||||
|
|
||||||
|
printk_debug("Configuring PCIe PEXs\n");
|
||||||
|
dump_south(dev);
|
||||||
|
|
||||||
|
/* Disable link. */
|
||||||
|
reg = pci_read_config8(dev, 0x50);
|
||||||
|
pci_write_config8(dev, 0x50, reg | 0x10);
|
||||||
|
|
||||||
|
/* Award has 0xb, VIA recommends 0x4. */
|
||||||
|
pci_write_config8(dev, 0xe1, 0xb);
|
||||||
|
/* Set replay timer limit. */
|
||||||
|
pci_write_config8(dev, 0xb1, 0xf0);
|
||||||
|
|
||||||
|
/* Enable link. */
|
||||||
|
reg = pci_read_config8(dev, 0x50);
|
||||||
|
pci_write_config8(dev, 0x50, reg & ~0x10);
|
||||||
|
|
||||||
|
/* Retrain. */
|
||||||
|
reg = pci_read_config8(dev, 0x50);
|
||||||
|
pci_write_config8(dev, 0x50, reg | 0x20);
|
||||||
|
|
||||||
|
reg = pci_read_config8(dev, 0x3e);
|
||||||
|
reg |= 0x40; /* Bus reset. */
|
||||||
|
pci_write_config8(dev, 0x3e, reg);
|
||||||
|
|
||||||
|
reg = pci_read_config8(dev, 0x3e);
|
||||||
|
reg &= ~0x40; /* Clear reset. */
|
||||||
|
pci_write_config8(dev, 0x3e, reg);
|
||||||
|
|
||||||
|
dump_south(dev);
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct device_operations peg_ops = {
|
||||||
|
.read_resources = pci_bus_read_resources,
|
||||||
|
.set_resources = pci_dev_set_resources,
|
||||||
|
.enable_resources = pci_bus_enable_resources,
|
||||||
|
.enable = peg_init,
|
||||||
|
.scan_bus = pciexp_scan_bridge,
|
||||||
|
.reset_bus = pci_bus_reset,
|
||||||
|
.ops_pci = 0,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct device_operations pcie_ops = {
|
||||||
|
.read_resources = pci_bus_read_resources,
|
||||||
|
.set_resources = pci_dev_set_resources,
|
||||||
|
.enable_resources = pci_bus_enable_resources,
|
||||||
|
.enable = pcie_init,
|
||||||
|
.scan_bus = pciexp_scan_bridge,
|
||||||
|
.reset_bus = pci_bus_reset,
|
||||||
|
.ops_pci = 0,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct pci_driver northbridge_driver __pci_driver = {
|
||||||
|
.ops = &peg_ops,
|
||||||
|
.vendor = PCI_VENDOR_ID_VIA,
|
||||||
|
.device = PCI_DEVICE_ID_VIA_K8T890CE_PEG,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct pci_driver pcie_drvd3f0 __pci_driver = {
|
||||||
|
.ops = &pcie_ops,
|
||||||
|
.vendor = PCI_VENDOR_ID_VIA,
|
||||||
|
.device = PCI_DEVICE_ID_VIA_K8T890CE_PEX0,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct pci_driver pcie_drvd3f1 __pci_driver = {
|
||||||
|
.ops = &pcie_ops,
|
||||||
|
.vendor = PCI_VENDOR_ID_VIA,
|
||||||
|
.device = PCI_DEVICE_ID_VIA_K8T890CE_PEX1,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct pci_driver pcie_drvd3f2 __pci_driver = {
|
||||||
|
.ops = &pcie_ops,
|
||||||
|
.vendor = PCI_VENDOR_ID_VIA,
|
||||||
|
.device = PCI_DEVICE_ID_VIA_K8T890CE_PEX2,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct pci_driver pcie_drvd3f3 __pci_driver = {
|
||||||
|
.ops = &pcie_ops,
|
||||||
|
.vendor = PCI_VENDOR_ID_VIA,
|
||||||
|
.device = PCI_DEVICE_ID_VIA_K8T890CE_PEX3,
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,121 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the LinuxBIOS project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License v2 as published by
|
||||||
|
* the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <device/device.h>
|
||||||
|
#include <device/pci.h>
|
||||||
|
#include <device/pci_ops.h>
|
||||||
|
#include <device/pci_ids.h>
|
||||||
|
#include <console/console.h>
|
||||||
|
|
||||||
|
#include "k8t890.h"
|
||||||
|
|
||||||
|
void mmconfig_set_resources(device_t dev)
|
||||||
|
{
|
||||||
|
struct resource *resource;
|
||||||
|
u8 reg;
|
||||||
|
|
||||||
|
resource = find_resource(dev, K8T890_MMCONFIG_MBAR);
|
||||||
|
if (resource) {
|
||||||
|
report_resource_stored(dev, resource, "<mmconfig>");
|
||||||
|
|
||||||
|
/* Remember this resource has been stored. */
|
||||||
|
resource->flags |= IORESOURCE_STORED;
|
||||||
|
pci_write_config8(dev, K8T890_MMCONFIG_MBAR,
|
||||||
|
(resource->base >> 28));
|
||||||
|
reg = pci_read_config8(dev, 0x60);
|
||||||
|
reg |= 0x3;
|
||||||
|
/* Enable MMCONFIG decoding. */
|
||||||
|
pci_write_config8(dev, 0x60, reg);
|
||||||
|
}
|
||||||
|
pci_dev_set_resources(dev);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void apic_mmconfig_read_resources(device_t dev)
|
||||||
|
{
|
||||||
|
struct resource *res;
|
||||||
|
pci_dev_read_resources(dev);
|
||||||
|
|
||||||
|
res = new_resource(dev, 0x40);
|
||||||
|
/* NB APIC fixed to this address. */
|
||||||
|
res->base = K8T890_APIC_BASE;
|
||||||
|
res->size = 256;
|
||||||
|
res->limit = res->base + res->size - 1;
|
||||||
|
res->align = 8;
|
||||||
|
res->gran = 8;
|
||||||
|
res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
|
||||||
|
IORESOURCE_STORED | IORESOURCE_ASSIGNED;
|
||||||
|
|
||||||
|
/* Add an MMCONFIG resource. */
|
||||||
|
res = new_resource(dev, K8T890_MMCONFIG_MBAR);
|
||||||
|
res->size = 256 * 1024 * 1024;
|
||||||
|
res->align = log2(res->size);
|
||||||
|
res->gran = log2(res->size);
|
||||||
|
res->limit = 0xffffffff; /* 4G */
|
||||||
|
res->flags = IORESOURCE_MEM;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void traf_ctrl_enable(struct device *dev)
|
||||||
|
{
|
||||||
|
volatile u32 *apic;
|
||||||
|
u32 data;
|
||||||
|
|
||||||
|
/* Enable D3F1-D3F3, no device2 redirect, enable just one device behind
|
||||||
|
* bridge device 2 and device 3).
|
||||||
|
*/
|
||||||
|
pci_write_config8(dev, 0x60, 0x88);
|
||||||
|
|
||||||
|
/* Will enable MMCONFIG later. */
|
||||||
|
pci_write_config8(dev, 0x64, 0x23);
|
||||||
|
/* No extended RCRB Base Address. */
|
||||||
|
pci_write_config8(dev, 0x62, 0x00);
|
||||||
|
|
||||||
|
/* Offset80 ->95 bit 4 in 1 in Award. */
|
||||||
|
|
||||||
|
/* Enable APIC, to K8T890_APIC_BASE. */
|
||||||
|
pci_write_config8(dev, 0x41, 0x00);
|
||||||
|
pci_write_config8(dev, 0x40, 0x8c);
|
||||||
|
/* BT_INTR enable, APIC Nonshare Mode Enable. */
|
||||||
|
pci_write_config8(dev, 0x42, 0x5);
|
||||||
|
|
||||||
|
apic = (u32 *)K8T890_APIC_BASE;
|
||||||
|
|
||||||
|
/* Set APIC to FSB transported messages. */
|
||||||
|
apic[0] = 3;
|
||||||
|
data = apic[4];
|
||||||
|
apic[4] = (data & 0xFFFFFE) | 1;
|
||||||
|
|
||||||
|
/* Set APIC ID. */
|
||||||
|
apic[0] = 0;
|
||||||
|
data = apic[4];
|
||||||
|
apic[4] = (data & 0xF0FFFF) | (K8T890_APIC_ID << 24);
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct device_operations traf_ctrl_ops = {
|
||||||
|
.read_resources = apic_mmconfig_read_resources,
|
||||||
|
.set_resources = mmconfig_set_resources,
|
||||||
|
.enable_resources = pci_dev_enable_resources,
|
||||||
|
.enable = traf_ctrl_enable,
|
||||||
|
.ops_pci = 0,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct pci_driver northbridge_driver __pci_driver = {
|
||||||
|
.ops = &traf_ctrl_ops,
|
||||||
|
.vendor = PCI_VENDOR_ID_VIA,
|
||||||
|
.device = PCI_DEVICE_ID_VIA_K8T890CE_5,
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,61 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the LinuxBIOS project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2004 Tyan Computer
|
||||||
|
* (Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer)
|
||||||
|
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* This file constructs the ROM strap table for K8T890. */
|
||||||
|
|
||||||
|
.section ".romstrap", "a", @progbits
|
||||||
|
|
||||||
|
.globl __romstrap_start
|
||||||
|
.globl __romstrap_end
|
||||||
|
|
||||||
|
__romstrap_start:
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Below are some Dev0 Func2 HT control registers values,
|
||||||
|
* depending on strap pin, one of below lines is used.
|
||||||
|
*/
|
||||||
|
tblpointer:
|
||||||
|
.long 0x504400AA, 0x61970FC2 //;200M
|
||||||
|
.long 0x504400AA, 0x61970FC2 //;400M
|
||||||
|
.long 0x504400AA, 0x61970FC2 //;600M
|
||||||
|
.long 0x504400AA, 0x61970FC2 //;800M
|
||||||
|
.long 0x504400AA, 0x61970FC2 //;1000M
|
||||||
|
.long 0x0
|
||||||
|
.long 0x0
|
||||||
|
.long 0x0
|
||||||
|
.long 0x0
|
||||||
|
.long 0x0
|
||||||
|
.long 0x0
|
||||||
|
.long 0x0
|
||||||
|
.long 0x0
|
||||||
|
.long 0x0
|
||||||
|
.long 0x0
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The pointer to above table should be at 0xffffd,
|
||||||
|
* the table itself MUST be aligned to 128B it seems!
|
||||||
|
*/
|
||||||
|
.long tblpointer - 0xFFF00000
|
||||||
|
|
||||||
|
__romstrap_end:
|
||||||
|
|
||||||
|
.previous
|
||||||
|
|
@ -0,0 +1,29 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the LinuxBIOS project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2007 AMD
|
||||||
|
* (Written by Yinghai Lu <yinghai.lu@amd.com> for AMD)
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Modified for K8T890 ROM strap by Rudolf Marek <r.marek@assembler.cz>. */
|
||||||
|
|
||||||
|
SECTIONS {
|
||||||
|
. = (_ROMBASE + ROM_IMAGE_SIZE - 0x2c) - (__romstrap_end - __romstrap_start);
|
||||||
|
.romstrap (.): {
|
||||||
|
*(.romstrap)
|
||||||
|
}
|
||||||
|
}
|
||||||
Loading…
Reference in New Issue