google/chell : update DPTF policy settings

Fine tuned DPTF policy values for chell device as below,
1. Increase Passive temperature value to 52 degree Celsius for TSR2.
2. Remove charger effect for TSR2.
3. Increase Minimum PowerLimit1 to 3W.
4. Reduce Maximum PowerLimit1 to 6W.

BUG=chrome-os-partner:54718
BRANCH=None.
TEST=Built for chell device.

Change-Id: I46f69e3cd527ea3d28bdd7daa29d91f76770c277
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/17376
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Sumeet Pawnikar 2016-11-11 13:32:48 +05:30 committed by Martin Roth
parent 8b3004e2fc
commit 1d6957e9a9
1 changed files with 3 additions and 6 deletions

View File

@ -29,7 +29,7 @@
#define DPTF_TSR2_SENSOR_ID 3
#define DPTF_TSR2_SENSOR_NAME "DRAM"
#define DPTF_TSR2_PASSIVE 51
#define DPTF_TSR2_PASSIVE 52
#define DPTF_TSR2_CRITICAL 75
#define DPTF_TSR3_SENSOR_ID 4
@ -65,9 +65,6 @@ Name (DTRT, Package () {
/* CPU Effect on Temp Sensor 2 */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 90, 0, 0, 0, 0 },
/* Charger Effect on Temp Sensor 2 */
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 600, 0, 0, 0, 0 },
/* CPU Effect on Temp Sensor 3 */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 },
})
@ -77,8 +74,8 @@ Name (MPPC, Package ()
0x2, /* Revision */
Package () { /* Power Limit 1 */
0, /* PowerLimitIndex, 0 for Power Limit 1 */
2500, /* PowerLimitMinimum */
7000, /* PowerLimitMaximum */
3000, /* PowerLimitMinimum */
6000, /* PowerLimitMaximum */
1000, /* TimeWindowMinimum */
1000, /* TimeWindowMaximum */
250 /* StepSize */