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coreboot-kgpe-d16
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Split the two usages of __ROMCC__: 

__ROMCC__ now means "Don't use prototypes, since romcc doesn't support them."
__PRE_RAM__ means "Use simpler versions of functions, and no device tree."

There are probably some places where both are tested, but only one is needed.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4921 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson 2009-11-06 17:02:51 +00:00
parent 637309d65e
commit 1d6d45e3c9
108 changed files with 148 additions and 242 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/i386/include/arch/cpu.h
View File

@ -104,7 +104,7 @@ static inline unsigned int cpuid_edx(unsigned int op)
#define X86_VENDOR_SIS 10
#define X86_VENDOR_UNKNOWN 0xff
#if !defined( __ROMCC__ ) && defined( __GNUC__)
#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) && defined( __GNUC__)
#include <device/device.h>

2
src/arch/i386/include/arch/hlt.h
View File

@ -1,7 +1,7 @@
#ifndef ARCH_HLT_H
#define ARCH_HLT_H
#if defined( __ROMCC__) && !defined(__GNUC__)
#if defined( __ROMCC__) && !defined(__PRE_RAM__) && !defined(__GNUC__)
static void hlt(void)
{
__builtin_hlt();

2
src/arch/i386/include/arch/io.h
View File

@ -9,7 +9,7 @@
* (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
* versions of the single-IO instructions (inb_p/inw_p/..).
*/
#if defined( __ROMCC__ ) && !defined (__GNUC__)
#if defined( __ROMCC__ ) && !defined (__GNUC__)
static inline void outb(uint8_t value, uint16_t port)
{
__builtin_outb(value, port);

2
src/arch/i386/lib/console_print.c
View File

@ -66,7 +66,7 @@ static void __console_tx_string(int loglevel, const char *str)
* set in some auto.c files to trigger the simple device_t version to be used.
* So __GNUCC__ does the right thing here.
*/
#if defined (__GNUCC__)
#if defined (__ROMCC__)
#define STATIC
#else
#define STATIC static

2
src/cpu/amd/dualcore/dualcore_id.c
View File

@ -2,7 +2,7 @@
#include <arch/cpu.h>
#include <cpu/amd/dualcore.h>
#ifdef __ROMCC__
#ifdef __PRE_RAM__
#include <cpu/amd/model_fxx_msr.h>
#endif

2
src/cpu/amd/microcode/microcode.c
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __ROMCC__
#ifndef __PRE_RAM__
#include <stdint.h>
#include <console/console.h>

4
src/cpu/amd/model_10xxx/apic_timer.c
View File

@ -23,8 +23,8 @@
#include <cpu/x86/lapic.h>
/* NOTE: We use the APIC TIMER register is to hold flags for AP init during
* pre-memory init (ROMCC). Don't use init_timer() and udelay is redirected
* to udelay_tsc().
* pre-memory init (__PRE_RAM__). Don't use init_timer() and udelay is
* redirected to udelay_tsc().
*/

4
src/cpu/amd/model_10xxx/update_microcode.c
View File

@ -18,7 +18,7 @@
*/
#ifndef __ROMCC__
#ifndef __PRE_RAM__
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
@ -29,7 +29,7 @@
static const u8 microcode_updates[] __attribute__ ((aligned(16))) = {
#ifdef __ROMCC__
#ifdef __PRE_RAM__
/* From the Revision Guide :
* Equivalent Processor Table for AMD Family 10h Processors

2
src/cpu/amd/quadcore/quadcore_id.c
View File

@ -20,7 +20,7 @@
#include <arch/cpu.h>
#include <cpu/amd/quadcore.h>
#ifdef __ROMCC__
#ifdef __PRE_RAM__
#include <cpu/amd/model_10xxx_msr.h>
#endif

2
src/cpu/x86/smm/smmrelocate.S
View File

@ -22,7 +22,7 @@
#include <arch/asm.h>
// Make sure no stage 2 code is included:
#define __ROMCC__
#define __PRE_RAM__
// FIXME: Is this piece of code southbridge specific, or
// can it be cleaned up so this include is not required?

1
src/drivers/pci/Makefile.inc
View File

@ -1 +0,0 @@
subdirs-y += onboard

4
src/drivers/pci/onboard/Config.lb
View File

@ -1,4 +0,0 @@
config chip.h
object onboard.o

1
src/drivers/pci/onboard/Makefile.inc
View File

@ -1 +0,0 @@
obj-y += onboard.o

11
src/drivers/pci/onboard/chip.h
View File

@ -1,11 +0,0 @@
#ifndef PCI_ONBOARD_H
#define PCI_ONBOARD_H
struct drivers_pci_onboard_config
{
unsigned long rom_address;
};
struct chip_operations;
extern struct chip_operations drivers_pci_onboard_ops;
#endif

78
src/drivers/pci/onboard/onboard.c
View File

@ -1,78 +0,0 @@
/*
* Copyright 2004 Tyan Computer
* by yhlu@tyan.com
*/
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "chip.h"
/*
* How to use the onboard device driver for option rom execution:
*
* 1. You need to add the driver to your mainboard Config.lb:
*
* chip drivers/pci/onboard
* device pci x.0 on end
* register "rom_address" = "0xfff80000"
* end
* 2. Reduce the size of your normal (or fallback) image, by adding the
* following lines to your target Config.lb, after romimage "normal"
* # 48K for SCSI FW or ATI ROM
* option CONFIG_ROM_SIZE = 512*1024-48*1024
* 3. Create your vgabios.bin, for example using awardeco and put it in the
* directory of your target Config.lb. You can also read an option rom from
* a running system, but this is unreliable, as some option roms are changed
* during execution:
* # dd if=/dev/mem of=atix.rom skip=1536 count=96
* 4. After you built coreboot.rom, attach the option rom to your coreboot
* image:
* # cat ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > coreboot.rom
*
* Alternatively you can use the following script "nsxv" to build your image
* Usage:
* # ./nsxv s2850
*
* #!/bin/bash
* MBVENDOR=tyan
* MBMODEL=$1
* LBROOT=/home/yhlu/xx/xx
*
* echo $1
* date
*
* cd "$LBROOT/freebios2/targets"
* rm -rf "$MBVENDOR/$MBMODEL/$MBMODEL"
* ./buildtarget "$MBVENDOR/$MBMODEL" &> "$LBROOT/x_b.txt"
* cd "$MBVENDOR/$MBMODEL/$MBMODEL"
* #make clean
* eval make &> "$LBROOT/x_m.txt"
* if [ $? -eq 0 ]; then
* echo "ok."
* else
* echo "FAILED! Log excerpt:"
* tail -n 15 "$LBROOT/x_m.txt"
* exit
* fi
* cat ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > "$LBROOT/rom/"$MBMODEL"_coreboot.rom"
* cp -f "$LBROOT/rom/"$MBMODEL"_coreboot.rom" /home/yhlu/
*
* date
*
*/
static void onboard_enable(device_t dev)
{
struct drivers_pci_onboard_config *conf;
conf = dev->chip_info;
dev->rom_address = conf->rom_address;
}
struct chip_operations drivers_pci_onboard_ops = {
CHIP_NAME("Onboard PCI")
.enable_dev = onboard_enable,
};

4
src/include/assert.h
View File

@ -24,7 +24,7 @@
// ROMCC doesn't support __FILE__ or __LINE__ :^{
#if CONFIG_DEBUG
#ifdef __ROMCC__
#ifdef __PRE_RAM__
#define ASSERT(x) { if (!(x)) die("ASSERT failure!\r\n"); }
#else
#define ASSERT(x) { \
@ -39,7 +39,7 @@
#define ASSERT(x) { }
#endif
#ifdef __ROMCC__
#ifdef __PRE_RAM__
#define BUG() { die("BUG encountered: system halted\r\n"); }
#else
#define BUG() { \

2
src/include/cpu/amd/dualcore.h
View File

@ -15,7 +15,7 @@ struct node_core_id {
struct node_core_id get_node_core_id(unsigned int nb_cfg_54);
#endif
#ifndef __ROMCC__
#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
struct device;
unsigned get_apicid_base(unsigned ioapic_num);
void amd_sibling_init(struct device *cpu);

4
src/include/cpu/amd/model_fxx_rev.h
View File

@ -49,7 +49,7 @@ static inline int is_cpu_e0(void)
}
#ifdef __ROMCC__
#ifdef __PRE_RAM__
static int is_e0_later_in_bsp(int nodeid)
{
uint32_t val;
@ -96,7 +96,7 @@ static inline int is_cpu_pre_f2(void)
return (cpuid_eax(1) & 0xfff0f) < 0x40f02;
}
#ifdef __ROMCC__
#ifdef __PRE_RAM__
//AMD_F0_SUPPORT
static int is_cpu_f0_in_bsp(int nodeid)
{

2
src/include/cpu/amd/mtrr.h
View File

@ -31,7 +31,7 @@
#define TOP_MEM_MASK 0x007fffff
#define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10)
#if !defined( __ROMCC__ ) && !defined (ASSEMBLY)
#if !defined( __ROMCC__ ) && !defined (ASSEMBLY) && !defined(__PRE_RAM__)
void amd_setup_mtrrs(void);
#endif /* __ROMCC__ */

2
src/include/cpu/amd/quadcore.h
View File

@ -34,7 +34,7 @@ struct node_core_id {
struct node_core_id get_node_core_id(u32 nb_cfg_54);
#endif
#ifndef __ROMCC__
#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
struct device;
u32 get_apicid_base(u32 ioapic_num);
void amd_sibling_init(struct device *cpu);

2
src/include/cpu/x86/cache.h
View File

@ -41,7 +41,7 @@ static inline void disable_cache(void)
wbinvd();
}
#if !defined( __ROMCC__) && defined (__GNUC__)
#if !defined( __ROMCC__) && !defined(__PRE_RAM__) && defined (__GNUC__)
void x86_enable_cache(void);
#endif /* !__ROMCC__ */

4
src/include/cpu/x86/lapic.h
View File

@ -68,7 +68,7 @@ static inline __attribute__((always_inline)) void stop_this_cpu(void)
}
#endif
#if ! defined (__ROMCC__)
#if ! defined (__ROMCC__) && !defined(__PRE_RAM__)
#define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
@ -157,6 +157,6 @@ int start_cpu(struct device *cpu);
#endif /* CONFIG_SMP */
#endif /* !__ROMCC__ */
#endif /* !__ROMCC__ && !__PRE_RAM__ */
#endif /* CPU_X86_LAPIC_H */

4
src/include/cpu/x86/msr.h
View File

@ -1,7 +1,7 @@
#ifndef CPU_X86_MSR_H
#define CPU_X86_MSR_H
#if defined( __ROMCC__) && !defined (__GNUC__)
#if defined( __ROMCC__)
typedef __builtin_msr_t msr_t;
@ -43,7 +43,7 @@ static inline void wrmsr(unsigned index, msr_t msr)
);
}
#endif /* ROMCC__ && !__GNUC__ */
#endif /* __ROMCC__ */
#endif /* CPU_X86_MSR_H */

2
src/include/cpu/x86/mtrr.h
View File

@ -32,7 +32,7 @@
#define MTRRfix4K_F8000_MSR 0x26f
#if !defined(__ROMCC__) && !defined (ASSEMBLY)
#if !defined(__ROMCC__) && !defined (ASSEMBLY) && !defined(__PRE_RAM__)
#include <device/device.h>

2
src/include/cpu/x86/tsc.h
View File

@ -17,7 +17,7 @@ static tsc_t rdtsc(void)
return res;
}
#ifndef __ROMCC__
#if !defined( __ROMCC__ ) && !defined (__PRE_RAM__)
static inline unsigned long long rdtscll(void)
{
unsigned long long val;

2
src/include/stdlib.h
View File

@ -11,7 +11,7 @@
#define MIN(a,b) ((a) < (b) ? (a) : (b))
#define MAX(a,b) ((a) > (b) ? (a) : (b))
#ifndef __ROMCC__
#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
void *malloc(size_t size);
void free(void *ptr);
#endif

4
src/include/string.h
View File

@ -8,7 +8,7 @@ void *memcpy(void *dest, const void *src, size_t n);
void *memmove(void *dest, const void *src, size_t n);
void *memset(void *s, int c, size_t n);
int memcmp(const void *s1, const void *s2, size_t n);
#ifndef __ROMCC__
#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
int sprintf(char * buf, const char *fmt, ...);
#endif
@ -41,7 +41,7 @@ static inline char *strchr(const char *s, int c)
return 0;
}
#ifndef __ROMCC__
#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
static inline char *strdup(const char *s)
{
size_t sz = strlen(s) + 1;

16
src/lib/cbmem.c
View File

@ -45,7 +45,7 @@ struct cbmem_entry {
u64 size;
} __attribute__((packed));
#ifndef __ROMCC__
#ifndef __PRE_RAM__
struct cbmem_entry *bss_cbmem_toc;
#endif
@ -64,7 +64,7 @@ void cbmem_init(u64 baseaddr, u64 size)
struct cbmem_entry *cbmem_toc;
cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr;
#ifndef __ROMCC__
#ifndef __PRE_RAM__
bss_cbmem_toc = cbmem_toc;
#endif
@ -91,7 +91,7 @@ int cbmem_reinit(u64 baseaddr)
cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr;
debug("Re-Initializing CBMEM area to 0x%lx\n", (unsigned long)baseaddr);
#ifndef __ROMCC__
#ifndef __PRE_RAM__
bss_cbmem_toc = cbmem_toc;
#endif
@ -102,7 +102,7 @@ void *cbmem_add(u32 id, u64 size)
{
struct cbmem_entry *cbmem_toc;
int i;
#ifdef __ROMCC__
#ifdef __PRE_RAM__
cbmem_toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
#else
cbmem_toc = bss_cbmem_toc;
@ -158,7 +158,7 @@ void *cbmem_find(u32 id)
{
struct cbmem_entry *cbmem_toc;
int i;
#ifdef __ROMCC__
#ifdef __PRE_RAM__
cbmem_toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
#else
cbmem_toc = bss_cbmem_toc;
@ -175,7 +175,7 @@ void *cbmem_find(u32 id)
return (void *)NULL;
}
#ifndef __ROMCC__
#ifndef __PRE_RAM__
#if CONFIG_HAVE_ACPI_RESUME
extern u8 acpi_slp_type;
#endif
@ -199,12 +199,12 @@ void cbmem_initialize(void)
cbmem_arch_init();
}
#ifndef __ROMCC__
#ifndef __PRE_RAM__
void cbmem_list(void)
{
struct cbmem_entry *cbmem_toc;
int i;
#ifdef __ROMCC__
#ifdef __PRE_RAM__
cbmem_toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
#else
cbmem_toc = bss_cbmem_toc;

2
src/lib/usbdebug_direct.c
View File

@ -19,7 +19,7 @@
/*
* 2006.12.10 yhlu moved it to corbeoot and use struct instead
*/
#ifndef __ROMCC__
#if !defined(__ROMCC__)
#include <console/console.h>
#else
#if CONFIG_USE_PRINTK_IN_CAR==0

2
src/mainboard/amd/dbm690t/cache_as_ram_auto.c
View File

@ -18,7 +18,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1

2
src/mainboard/amd/pistachio/cache_as_ram_auto.c
View File

@ -18,7 +18,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1

2
src/mainboard/amd/serengeti_cheetah/apc_auto.c
View File

@ -1,5 +1,5 @@
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0

2
src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c
View File

@ -1,5 +1,5 @@
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0

2
src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c
View File

@ -18,7 +18,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0

2
src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c
View File

@ -19,7 +19,7 @@
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define SYSTEM_TYPE 0 /* SERVER */
//#define SYSTEM_TYPE 1 /* DESKTOP */

2
src/mainboard/arima/hdama/cache_as_ram_auto.c
View File

@ -1,5 +1,5 @@
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#include <stdint.h>
#include <device/pci_def.h>

2
src/mainboard/asus/a8n_e/cache_as_ram_auto.c
View File

@ -22,7 +22,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
/* Used by it8712f_enable_serial(). */
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)

2
src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c
View File

@ -23,7 +23,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1

2
src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c
View File

@ -23,7 +23,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1

2
src/mainboard/broadcom/blast/cache_as_ram_auto.c
View File

@ -1,5 +1,5 @@
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define QRANK_DIMM_SUPPORT 1

2
src/mainboard/dell/s1850/reset.c
View File

@ -2,7 +2,7 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#ifndef __ROMCC__
#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
#include <device/pci.h>
#define PCI_ID(VENDOR_ID, DEVICE_ID) \
((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))

2
src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c
View File

@ -22,7 +22,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0

2
src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c
View File

@ -22,7 +22,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1

2
src/mainboard/gigabyte/m57sli/apc_auto.c
View File

@ -20,7 +20,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0

2
src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
View File

@ -20,7 +20,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1

2
src/mainboard/hp/dl145_g3/cache_as_ram_auto.c
View File

@ -26,7 +26,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1

2
src/mainboard/ibm/e325/cache_as_ram_auto.c
View File

@ -1,5 +1,5 @@
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#include <stdint.h>
#include <string.h>

2
src/mainboard/ibm/e326/cache_as_ram_auto.c
View File

@ -1,5 +1,5 @@
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#include <stdint.h>
#include <string.h>

8
src/mainboard/intel/d945gclf/auto.c
View File

@ -17,8 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
// __ROMCC__ means: use "unsigned" for device, not a struct.
#define __ROMCC__
// __PRE_RAM__ means: use "unsigned" for device, not a struct.
#define __PRE_RAM__
#include <stdint.h>
#include <string.h>
@ -220,10 +220,10 @@ static void early_ich7_init(void)
#include <cbmem.h>
// Now, this needs to be included because it relies on the symbol
// __ROMCC_ being set during CAR stage (in order to compile the
// __PRE_RAM__ being set during CAR stage (in order to compile the
// BSS free versions of the functions). Either rewrite the code
// to be always BSS free, or invent a flag that's better suited than
// __ROMCC__ to determine whether we're in ram init stage (stage 1)
// __PRE_RAM__ to determine whether we're in ram init stage (stage 1)
//
#include "lib/cbmem.c"

2
src/mainboard/intel/eagleheights/auto.c
View File

@ -20,7 +20,7 @@
* MA 02110-1301 USA
*/
#define __ROMCC__
#define __PRE_RAM__
#include <delay.h>

2
src/mainboard/intel/eagleheights/reset.c
View File

@ -22,7 +22,7 @@
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#ifndef __ROMCC__
#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>

2
src/mainboard/intel/jarrell/reset.c
View File

@ -1,7 +1,7 @@
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#ifndef __ROMCC__
#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>

1
src/mainboard/intel/xe7501devkit/auto.c
View File

@ -1,4 +1,5 @@
#define ASSEMBLY 1
#define __PRE_RAM__
#include <stdint.h>
#include <device/pci_def.h>

2
src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c
View File

@ -1,5 +1,5 @@
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0

2
src/mainboard/iwill/dk8s2/cache_as_ram_auto.c
View File

@ -1,5 +1,5 @@
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0

2
src/mainboard/iwill/dk8x/cache_as_ram_auto.c
View File

@ -1,5 +1,5 @@
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0

8
src/mainboard/kontron/986lcd-m/auto.c
View File

@ -19,8 +19,8 @@
* MA 02110-1301 USA
*/
// __ROMCC__ means: use "unsigned" for device, not a struct.
#define __ROMCC__
// __PRE_RAM__ means: use "unsigned" for device, not a struct.
#define __PRE_RAM__
#include <stdint.h>
#include <string.h>
@ -359,10 +359,10 @@ static void early_ich7_init(void)
#include <cbmem.h>
// Now, this needs to be included because it relies on the symbol
// __ROMCC_ being set during CAR stage (in order to compile the
// __PRE_RAM__ being set during CAR stage (in order to compile the
// BSS free versions of the functions). Either rewrite the code
// to be always BSS free, or invent a flag that's better suited than
// __ROMCC__ to determine whether we're in ram init stage (stage 1)
// __PRE_RAM__ to determine whether we're in ram init stage (stage 1)
//
#include "lib/cbmem.c"

2
src/mainboard/kontron/kt690/cache_as_ram_auto.c
View File

@ -19,7 +19,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1

2
src/mainboard/msi/ms7135/cache_as_ram_auto.c
View File

@ -23,7 +23,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define SERIAL_DEV PNP_DEV(0x4e, W83627HF_SP1)

2
src/mainboard/msi/ms7260/apc_auto.c
View File

@ -21,7 +21,7 @@
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0

2
src/mainboard/msi/ms7260/cache_as_ram_auto.c
View File

@ -21,7 +21,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
// #define CACHE_AS_RAM_ADDRESS_DEBUG 1
// #define DEBUG_SMBUS 1

2
src/mainboard/msi/ms9185/cache_as_ram_auto.c
View File

@ -24,7 +24,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0

2
src/mainboard/msi/ms9282/cache_as_ram_auto.c
View File

@ -23,7 +23,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0

2
src/mainboard/newisys/khepri/cache_as_ram_auto.c
View File

@ -4,7 +4,7 @@
* Additional (C) 2007 coresystems GmbH
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#include <stdint.h>
#include <string.h>

2
src/mainboard/nvidia/l1_2pvv/apc_auto.c
View File

@ -20,7 +20,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0

2
src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c
View File

@ -20,7 +20,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1

2
src/mainboard/sunw/ultra40/cache_as_ram_auto.c
View File

@ -1,5 +1,5 @@
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define K8_ALLOCATE_IO_RANGE 1

2
src/mainboard/supermicro/h8dme/apc_auto.c
View File

@ -20,7 +20,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0

2
src/mainboard/supermicro/h8dme/cache_as_ram_auto.c
View File

@ -17,7 +17,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1

2
src/mainboard/supermicro/h8dmr/apc_auto.c
View File

@ -20,7 +20,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0

2
src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c
View File

@ -20,7 +20,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1

2
src/mainboard/supermicro/h8dmr_fam10/apc_auto.c
View File

@ -20,7 +20,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0

2
src/mainboard/supermicro/h8dmr_fam10/cache_as_ram_auto.c
View File

@ -20,7 +20,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1

2
src/mainboard/supermicro/x6dai_g/reset.c
View File

@ -1,7 +1,7 @@
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#ifndef __ROMCC__
#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>

2
src/mainboard/supermicro/x6dhe_g/reset.c
View File

@ -1,7 +1,7 @@
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#ifndef __ROMCC__
#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>

2
src/mainboard/supermicro/x6dhe_g2/reset.c
View File

@ -1,7 +1,7 @@
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#ifndef __ROMCC__
#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>

2
src/mainboard/supermicro/x6dhr_ig/reset.c
View File

@ -1,7 +1,7 @@
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#ifndef __ROMCC__
#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>

2
src/mainboard/supermicro/x6dhr_ig2/reset.c
View File

@ -1,7 +1,7 @@
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#ifndef __ROMCC__
#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>

2
src/mainboard/technexion/tim5690/cache_as_ram_auto.c
View File

@ -18,7 +18,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1

2
src/mainboard/technexion/tim8690/cache_as_ram_auto.c
View File

@ -18,7 +18,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1

2
src/mainboard/tyan/s2735/cache_as_ram_auto.c
View File

@ -1,5 +1,5 @@
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#include <stdint.h>
#include <string.h>

2
src/mainboard/tyan/s2850/cache_as_ram_auto.c
View File

@ -1,5 +1,5 @@
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#include <stdint.h>
#include <string.h>

2
src/mainboard/tyan/s2875/cache_as_ram_auto.c
View File

@ -1,5 +1,5 @@
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#include <stdint.h>
#include <string.h>

2
src/mainboard/tyan/s2880/cache_as_ram_auto.c
View File

@ -1,5 +1,5 @@
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#include <stdint.h>
#include <string.h>

2
src/mainboard/tyan/s2881/cache_as_ram_auto.c
View File

@ -1,5 +1,5 @@
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define QRANK_DIMM_SUPPORT 1

2
src/mainboard/tyan/s2882/cache_as_ram_auto.c
View File

@ -1,5 +1,5 @@
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#include <stdint.h>
#include <string.h>

2
src/mainboard/tyan/s2885/cache_as_ram_auto.c
View File

@ -1,5 +1,5 @@
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#include <stdint.h>
#include <string.h>

2
src/mainboard/tyan/s2891/cache_as_ram_auto.c
View File

@ -1,5 +1,5 @@
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
//used by raminit
#define QRANK_DIMM_SUPPORT 1

2
src/mainboard/tyan/s2892/cache_as_ram_auto.c
View File

@ -1,5 +1,5 @@
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define QRANK_DIMM_SUPPORT 1

2
src/mainboard/tyan/s2895/cache_as_ram_auto.c
View File

@ -1,5 +1,5 @@
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define K8_ALLOCATE_IO_RANGE 1

2
src/mainboard/tyan/s2895/failover.c
View File

@ -1,5 +1,5 @@
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#include <stdint.h>
#include <string.h>

2
src/mainboard/tyan/s2912/apc_auto.c
View File

@ -20,7 +20,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0

2
src/mainboard/tyan/s2912/cache_as_ram_auto.c
View File

@ -20,7 +20,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1

2
src/mainboard/tyan/s2912_fam10/apc_auto.c
View File

@ -20,7 +20,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0

2
src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c
View File

@ -20,7 +20,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1

2
src/mainboard/tyan/s4880/cache_as_ram_auto.c
View File

@ -1,5 +1,5 @@
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#include <stdint.h>
#include <string.h>

2
src/mainboard/tyan/s4882/cache_as_ram_auto.c
View File

@ -1,5 +1,5 @@
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#include <stdint.h>
#include <string.h>

2
src/mainboard/via/epia-m700/cache_as_ram_auto.c
View File

@ -23,7 +23,7 @@
*/
#define ASSEMBLY 1
#define __ROMCC__
#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0

8
src/northbridge/amd/amdfam10/amdfam10.h
View File

@ -956,7 +956,7 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
#include "amdfam10_nums.h"
#ifdef __ROMCC__
#ifdef __PRE_RAM__
#if NODE_NUMS==64
#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
#else
@ -1086,7 +1086,7 @@ struct sys_info {
#if CONFIG_AMDMCT == 0
#ifdef __ROMCC__
#ifdef __PRE_RAM__
static void soft_reset(void);
#endif
static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
@ -1131,7 +1131,7 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
}
for(i=0; i<sysinfo->nodes; i++) {
#ifdef __ROMCC__
#ifdef __PRE_RAM__
print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n");
#else
printk_debug("mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
@ -1148,7 +1148,7 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
}
}
if(needs_reset) {
#ifdef __ROMCC__
#ifdef __PRE_RAM__
print_debug("mem trained failed\n");
soft_reset();
#else

42
src/northbridge/amd/amdfam10/amdfam10_conf.c
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#if defined(__ROMCC__)
#if defined(__PRE_RAM__)
typedef struct sys_info sys_info_conf_t;
#else
typedef struct amdfam10_sysconf_t sys_info_conf_t;
@ -32,7 +32,7 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid)
{
device_t dev;
struct dram_base_mask_t d;
#if defined(__ROMCC__)
#if defined(__PRE_RAM__)
dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1);
#else
dev = __f1_dev[0];
@ -88,7 +88,7 @@ static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes)
#endif
for(i=0;i<nodes;i++) {
#if defined(__ROMCC__)
#if defined(__PRE_RAM__)
dev = NODE_PCI(i, 1);
#else
dev = __f1_dev[i];
@ -108,7 +108,7 @@ static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes)
#endif
}
#if defined(__ROMCC__)
#if defined(__PRE_RAM__)
dev = NODE_PCI(nodeid, 1);
#else
dev = __f1_dev[nodeid];
@ -122,7 +122,7 @@ static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes)
static void set_DctSelBaseAddr(u32 i, u32 sel_m)
{
device_t dev;
#if defined(__ROMCC__)
#if defined(__PRE_RAM__)
dev = NODE_PCI(i, 2);
#else
dev = __f2_dev[i];
@ -139,7 +139,7 @@ static void set_DctSelBaseAddr(u32 i, u32 sel_m)
static u32 get_DctSelBaseAddr(u32 i)
{
device_t dev;
#if defined(__ROMCC__)
#if defined(__PRE_RAM__)
dev = NODE_PCI(i, 2);
#else
dev = __f2_dev[i];
@ -156,7 +156,7 @@ static u32 get_DctSelBaseAddr(u32 i)
static void set_DctSelHiEn(u32 i, u32 val)
{
device_t dev;
#if defined(__ROMCC__)
#if defined(__PRE_RAM__)
dev = NODE_PCI(i, 2);
#else
dev = __f2_dev[i];
@ -172,7 +172,7 @@ static void set_DctSelHiEn(u32 i, u32 val)
static u32 get_DctSelHiEn(u32 i)
{
device_t dev;
#if defined(__ROMCC__)
#if defined(__PRE_RAM__)
dev = NODE_PCI(i, 2);
#else
dev = __f2_dev[i];
@ -187,7 +187,7 @@ static u32 get_DctSelHiEn(u32 i)
static void set_DctSelBaseOffset(u32 i, u32 sel_off_m)
{
device_t dev;
#if defined(__ROMCC__)
#if defined(__PRE_RAM__)
dev = NODE_PCI(i, 2);
#else
dev = __f2_dev[i];
@ -203,7 +203,7 @@ static void set_DctSelBaseOffset(u32 i, u32 sel_off_m)
static u32 get_DctSelBaseOffset(u32 i)
{
device_t dev;
#if defined(__ROMCC__)
#if defined(__PRE_RAM__)
dev = NODE_PCI(i, 2);
#else
dev = __f2_dev[i];
@ -264,7 +264,7 @@ static u32 hoist_memory(u32 hole_startk, u32 i, u32 one_DCT, u32 nodes)
d = get_dram_base_mask(i);
d.mask += (carry_over>>9);
set_dram_base_mask(i,d, nodes);
#if defined(__ROMCC__)
#if defined(__PRE_RAM__)
dev = NODE_PCI(i, 1);
#else
dev = __f1_dev[i];
@ -330,7 +330,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest,
index_max = busn_max>>2; dest_max = busn_max - (index_max<<2);
// three case: index_min==index_max, index_min+1=index_max; index_min+1<index_max
#if defined(__ROMCC__)
#if defined(__PRE_RAM__)
dev = NODE_PCI(nodeid, 1);
#else
dev = __f1_dev[nodeid];
@ -393,7 +393,7 @@ static void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
#endif
tempreg = 3 | ((nodeid&0xf)<<4) | ((nodeid & 0x30)<<(12-4))|(linkn<<8)|((busn_min & 0xff)<<16)|((busn_max&0xff)<<24);
for(i=0; i<nodes; i++) {
#if defined(__ROMCC__)
#if defined(__PRE_RAM__)
dev = NODE_PCI(i, 1);
#else
dev = __f1_dev[i];
@ -433,7 +433,7 @@ static void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
if(ht_c_index<4) {
#endif
for(i=0; i<nodes; i++) {
#if defined(__ROMCC__)
#if defined(__PRE_RAM__)
dev = NODE_PCI(i, 1);
#else
dev = __f1_dev[i];
@ -480,7 +480,7 @@ static u32 check_segn(device_t dev, u32 segbusn, u32 nodes,
}
#endif
#if defined(__ROMCC__)
#if defined(__PRE_RAM__)
static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
u32 io_min, u32 io_max, u32 nodes)
{
@ -494,7 +494,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
/* io range allocation */
tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit
for(i=0; i<nodes; i++) {
#if defined(__ROMCC__)
#if defined(__PRE_RAM__)
dev = NODE_PCI(i, 1);
#else
dev = __f1_dev[i];
@ -503,7 +503,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
}
tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
for(i=0; i<nodes; i++){
#if defined(__ROMCC__)
#if defined(__PRE_RAM__)
dev = NODE_PCI(i, 1);
#else
dev = __f1_dev[i];
@ -546,7 +546,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
#endif
/* io range allocation */
for(i=0; i<nodes; i++) {
#if defined(__ROMCC__)
#if defined(__PRE_RAM__)
dev = NODE_PCI(i, 1);
#else
dev = __f1_dev[i];
@ -584,7 +584,7 @@ static void re_set_all_config_map_reg(u32 nodes, u32 segbit,
for(ht_c_index=1;ht_c_index<4; ht_c_index++) {
u32 i;
for(i=0; i<nodes; i++) {
#if defined(__ROMCC__)
#if defined(__PRE_RAM__)
dev = NODE_PCI(i, 1);
#else
dev = __f1_dev[i];
@ -664,7 +664,7 @@ static void set_BusSegmentEn(u32 node, u32 segbit)
u32 dword;
device_t dev;
#if defined(__ROMCC__)
#if defined(__PRE_RAM__)
dev = NODE_PCI(node, 0);
#else
dev = __f0_dev[node];
@ -677,7 +677,7 @@ static void set_BusSegmentEn(u32 node, u32 segbit)
#endif
}
#if !defined(__ROMCC__)
#if !defined(__PRE_RAM__)
static u32 get_io_addr_index(u32 nodeid, u32 linkn)
{
u32 index;

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