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mb/google/rambi: Convert to use override devicetree 

Since the variants' devicetrees are almost identical, convert to
using an overridetree setup for simplicity.

Change-Id: I52b71cf12a4e0b67135cfb106c3e89b00205d3bc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39996
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Matt DeVillier 2020-03-31 17:37:12 -05:00
parent c0b028f205
commit 1d6e07348a
33 changed files with 158 additions and 1561 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/google/rambi/Kconfig
View File

@ -64,9 +64,9 @@ config MAINBOARD_PART_NUMBER
default "Swanky" if BOARD_GOOGLE_SWANKY
default "Winky" if BOARD_GOOGLE_WINKY
config DEVICETREE
config OVERRIDE_DEVICETREE
string
default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
config EC_GOOGLE_CHROMEEC_BOARDNAME
string

3
src/mainboard/google/rambi/variants/quawks/devicetree.cb → src/mainboard/google/rambi/devicetree.cb
View File

@ -13,7 +13,6 @@ chip soc/intel/baytrail
register "usb3_port_disable_mask" = "0x0"
# USB PHY settings
# TODO: These values are from Baytrail and need tuned for Quawks board
register "usb2_per_port_lane0" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
register "usb2_per_port_lane1" = "0x00049a09"
@ -74,7 +73,7 @@ chip soc/intel/baytrail
device pci 1a.0 off end # TXE
device pci 1b.0 on end # HDA
device pci 1c.0 on end # PCIE_PORT1
device pci 1c.1 on end # PCIE_PORT2
device pci 1c.1 off end # PCIE_PORT2
device pci 1c.2 off end # PCIE_PORT3
device pci 1c.3 off end # PCIE_PORT4
device pci 1d.0 on end # EHCI

104
src/mainboard/google/rambi/variants/banjo/devicetree.cb
View File

@ -1,104 +0,0 @@
chip soc/intel/baytrail
# SATA port enable mask (2 ports)
register "sata_port_map" = "0x1"
register "sata_ahci" = "0x1"
register "ide_legacy_combined" = "0x0"
# Route USB ports to XHCI
register "usb_route_to_xhci" = "1"
# USB Port Disable Mask
register "usb2_port_disable_mask" = "0x0"
register "usb3_port_disable_mask" = "0x0"
# USB PHY settings
# TODO: These values are from Baytrail and need tuned for Banjo board
register "usb2_per_port_lane0" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
register "usb2_per_port_lane1" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
register "usb2_per_port_lane2" = "0x00049209"
register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
register "usb2_per_port_lane3" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
# LPE audio codec settings
register "lpe_codec_clk_freq" = "25" # 25MHz clock
register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
# SD Card controller
register "sdcard_cap_low" = "0x0"
register "sdcard_cap_high" = "0x0"
# Enable devices in ACPI mode
register "lpe_acpi_mode" = "1"
register "lpss_acpi_mode" = "1"
register "scc_acpi_mode" = "1"
# Allow PCIe devices to wake system from suspend
register "pcie_wake_enable" = "1"
# Enable PIPEA as DP_C
register "gpu_pipea_port_select" = "2" # DP_C
register "gpu_pipea_power_cycle_delay" = "6" # 600ms
register "gpu_pipea_power_on_delay" = "5000" # 500ms
register "gpu_pipea_light_on_delay" = "70" # 7ms
register "gpu_pipea_power_off_delay" = "500" # 50ms
register "gpu_pipea_light_off_delay" = "2000" # 200ms
# VR PS2 control
register "vnn_ps2_enable" = "1"
register "vcc_ps2_enable" = "1"
# Disable SLP_X stretching after SUS power well fail.
register "disable_slp_x_stretch_sus_fail" = "1"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # SoC router
device pci 02.0 on end # GFX
device pci 11.0 off end # SDIO
device pci 12.0 off end # SD
device pci 13.0 on end # SATA
device pci 14.0 on end # XHCI
device pci 15.0 on end # LPE
device pci 17.0 on end # MMC
device pci 18.0 on end # SIO_DMA1
device pci 18.1 on end # I2C1
device pci 18.2 on end # I2C2
device pci 18.3 off end # I2C3
device pci 18.4 off end # I2C4
device pci 18.5 off end # I2C5
device pci 18.6 off end # I2C6
device pci 18.7 off end # I2C7
device pci 1a.0 off end # TXE
device pci 1b.0 on end # HDA
device pci 1c.0 on end # PCIE_PORT1
device pci 1c.1 off end # PCIE_PORT2
device pci 1c.2 off end # PCIE_PORT3
device pci 1c.3 off end # PCIE_PORT4
device pci 1d.0 on end # EHCI
device pci 1e.0 on end # SIO_DMA2
device pci 1e.1 off end # PWM1
device pci 1e.2 off end # PWM2
device pci 1e.3 off end # HSUART1
device pci 1e.4 off end # HSUART2
device pci 1e.5 off end # SPI
device pci 1f.0 on
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
chip ec/google/chromeec
# We only have one init function that
# we need to call to initialize the
# keyboard part of the EC.
device pnp ff.1 on # dummy address
end
end
end # LPC Bridge
device pci 1f.3 off end # SMBus
end
end

11
src/mainboard/google/rambi/variants/banjo/overridetree.cb Normal file
View File

@ -0,0 +1,11 @@
chip soc/intel/baytrail
register "sdcard_cap_low" = "0x0"
# Allow PCIe devices to wake system from suspend
register "pcie_wake_enable" = "1"
device domain 0 on
device pci 12.0 off end # SD
end
end

105
src/mainboard/google/rambi/variants/candy/devicetree.cb
View File

@ -1,105 +0,0 @@
chip soc/intel/baytrail
# SATA port enable mask (2 ports)
register "sata_port_map" = "0x1"
register "sata_ahci" = "0x1"
register "ide_legacy_combined" = "0x0"
# Route USB ports to XHCI
register "usb_route_to_xhci" = "1"
# USB Port Disable Mask
register "usb2_port_disable_mask" = "0x0"
register "usb3_port_disable_mask" = "0x0"
# USB PHY settings
# TODO: These values are from Baytrail and need tuned for Candy board
register "usb2_per_port_lane0" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
register "usb2_per_port_lane1" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
register "usb2_per_port_lane2" = "0x00049209"
register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
register "usb2_per_port_lane3" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
register "usb2_comp_bg" = "0x4700"
# LPE audio codec settings
register "lpe_codec_clk_freq" = "25" # 25MHz clock
register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
# SD Card controller
register "sdcard_cap_low" = "0x036864b2"
register "sdcard_cap_high" = "0x0"
# Enable devices in ACPI mode
register "lpe_acpi_mode" = "1"
register "lpss_acpi_mode" = "1"
register "scc_acpi_mode" = "1"
# Allow PCIe devices to wake system from suspend
register "pcie_wake_enable" = "1"
# Enable PIPEA as DP_C
register "gpu_pipea_port_select" = "2" # DP_C
register "gpu_pipea_power_cycle_delay" = "6" # 600ms
register "gpu_pipea_power_on_delay" = "5000" # 500ms
register "gpu_pipea_light_on_delay" = "70" # 7ms
register "gpu_pipea_power_off_delay" = "500" # 50ms
register "gpu_pipea_light_off_delay" = "2000" # 200ms
# VR PS2 control
register "vnn_ps2_enable" = "1"
register "vcc_ps2_enable" = "1"
# Disable SLP_X stretching after SUS power well fail.
register "disable_slp_x_stretch_sus_fail" = "1"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # SoC router
device pci 02.0 on end # GFX
device pci 11.0 off end # SDIO
device pci 12.0 on end # SD
device pci 13.0 on end # SATA
device pci 14.0 on end # XHCI
device pci 15.0 on end # LPE
device pci 17.0 on end # MMC
device pci 18.0 on end # SIO_DMA1
device pci 18.1 on end # I2C1
device pci 18.2 on end # I2C2
device pci 18.3 off end # I2C3
device pci 18.4 off end # I2C4
device pci 18.5 off end # I2C5
device pci 18.6 on end # I2C6
device pci 18.7 off end # I2C7
device pci 1a.0 off end # TXE
device pci 1b.0 on end # HDA
device pci 1c.0 on end # PCIE_PORT1
device pci 1c.1 off end # PCIE_PORT2
device pci 1c.2 off end # PCIE_PORT3
device pci 1c.3 off end # PCIE_PORT4
device pci 1d.0 on end # EHCI
device pci 1e.0 on end # SIO_DMA2
device pci 1e.1 off end # PWM1
device pci 1e.2 off end # PWM2
device pci 1e.3 off end # HSUART1
device pci 1e.4 off end # HSUART2
device pci 1e.5 off end # SPI
device pci 1f.0 on
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
chip ec/google/chromeec
# We only have one init function that
# we need to call to initialize the
# keyboard part of the EC.
device pnp ff.1 on # dummy address
end
end
end # LPC Bridge
device pci 1f.3 off end # SMBus
end
end

11
src/mainboard/google/rambi/variants/candy/overridetree.cb Normal file
View File

@ -0,0 +1,11 @@
chip soc/intel/baytrail
register "usb2_comp_bg" = "0x4700"
# Allow PCIe devices to wake system from suspend
register "pcie_wake_enable" = "1"
device domain 0 on
device pci 18.6 on end # I2C6
end
end

101
src/mainboard/google/rambi/variants/clapper/devicetree.cb
View File

@ -1,101 +0,0 @@
chip soc/intel/baytrail
# SATA port enable mask (2 ports)
register "sata_port_map" = "0x1"
register "sata_ahci" = "0x1"
register "ide_legacy_combined" = "0x0"
# Route USB ports to XHCI
register "usb_route_to_xhci" = "1"
# USB Port Disable Mask
register "usb2_port_disable_mask" = "0x0"
register "usb3_port_disable_mask" = "0x0"
# USB PHY settings
# TODO: These values are from Baytrail and need tuned for Clapper board
register "usb2_per_port_lane0" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
register "usb2_per_port_lane1" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
register "usb2_per_port_lane2" = "0x00049209"
register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
register "usb2_per_port_lane3" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
# LPE audio codec settings
register "lpe_codec_clk_freq" = "25" # 25MHz clock
register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
# SD Card controller
register "sdcard_cap_low" = "0x036864b2"
register "sdcard_cap_high" = "0x0"
# Enable devices in ACPI mode
register "lpe_acpi_mode" = "1"
register "lpss_acpi_mode" = "1"
register "scc_acpi_mode" = "1"
# Enable PIPEA as DP_C
register "gpu_pipea_port_select" = "2" # DP_C
register "gpu_pipea_power_cycle_delay" = "6" # 600ms
register "gpu_pipea_power_on_delay" = "5000" # 500ms
register "gpu_pipea_light_on_delay" = "70" # 7ms
register "gpu_pipea_power_off_delay" = "500" # 50ms
register "gpu_pipea_light_off_delay" = "2000" # 200ms
# VR PS2 control
register "vnn_ps2_enable" = "1"
register "vcc_ps2_enable" = "1"
# Disable SLP_X stretching after SUS power well fail.
register "disable_slp_x_stretch_sus_fail" = "1"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # SoC router
device pci 02.0 on end # GFX
device pci 11.0 off end # SDIO
device pci 12.0 on end # SD
device pci 13.0 on end # SATA
device pci 14.0 on end # XHCI
device pci 15.0 on end # LPE
device pci 17.0 on end # MMC
device pci 18.0 on end # SIO_DMA1
device pci 18.1 on end # I2C1
device pci 18.2 on end # I2C2
device pci 18.3 off end # I2C3
device pci 18.4 off end # I2C4
device pci 18.5 on end # I2C5
device pci 18.6 on end # I2C6
device pci 18.7 off end # I2C7
device pci 1a.0 off end # TXE
device pci 1b.0 on end # HDA
device pci 1c.0 on end # PCIE_PORT1
device pci 1c.1 on end # PCIE_PORT2
device pci 1c.2 off end # PCIE_PORT3
device pci 1c.3 off end # PCIE_PORT4
device pci 1d.0 on end # EHCI
device pci 1e.0 on end # SIO_DMA2
device pci 1e.1 off end # PWM1
device pci 1e.2 off end # PWM2
device pci 1e.3 off end # HSUART1
device pci 1e.4 off end # HSUART2
device pci 1e.5 off end # SPI
device pci 1f.0 on
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
chip ec/google/chromeec
# We only have one init function that
# we need to call to initialize the
# keyboard part of the EC.
device pnp ff.1 on # dummy address
end
end
end # LPC Bridge
device pci 1f.3 off end # SMBus
end
end

8
src/mainboard/google/rambi/variants/clapper/overridetree.cb Normal file
View File

@ -0,0 +1,8 @@
chip soc/intel/baytrail
device domain 0 on
device pci 18.5 on end # I2C5
device pci 18.6 on end # I2C6
device pci 1c.1 on end # PCIE_PORT2
end
end

104
src/mainboard/google/rambi/variants/enguarde/devicetree.cb
View File

@ -1,104 +0,0 @@
chip soc/intel/baytrail
# SATA port enable mask (2 ports)
register "sata_port_map" = "0x1"
register "sata_ahci" = "0x1"
register "ide_legacy_combined" = "0x0"
# Route USB ports to XHCI
register "usb_route_to_xhci" = "1"
# USB Port Disable Mask
register "usb2_port_disable_mask" = "0x0"
register "usb3_port_disable_mask" = "0x0"
# USB PHY settings
# TODO: These values are from Baytrail and need tuned for Enguarde board
register "usb2_per_port_lane0" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
register "usb2_per_port_lane1" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
register "usb2_per_port_lane2" = "0x00049209"
register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
register "usb2_per_port_lane3" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
# LPE audio codec settings
register "lpe_codec_clk_freq" = "25" # 25MHz clock
register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
# SD Card controller
register "sdcard_cap_low" = "0x036864b2"
register "sdcard_cap_high" = "0x0"
# Enable devices in ACPI mode
register "lpe_acpi_mode" = "1"
register "lpss_acpi_mode" = "1"
register "scc_acpi_mode" = "1"
# Allow PCIe devices to wake system from suspend
register "pcie_wake_enable" = "1"
# Enable PIPEA as DP_C
register "gpu_pipea_port_select" = "2" # DP_C
register "gpu_pipea_power_cycle_delay" = "6" # 600ms
register "gpu_pipea_power_on_delay" = "5000" # 500ms
register "gpu_pipea_light_on_delay" = "70" # 7ms
register "gpu_pipea_power_off_delay" = "500" # 50ms
register "gpu_pipea_light_off_delay" = "2000" # 200ms
# VR PS2 control
register "vnn_ps2_enable" = "1"
register "vcc_ps2_enable" = "1"
# Disable SLP_X stretching after SUS power well fail.
register "disable_slp_x_stretch_sus_fail" = "1"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # SoC router
device pci 02.0 on end # GFX
device pci 11.0 off end # SDIO
device pci 12.0 on end # SD
device pci 13.0 on end # SATA
device pci 14.0 on end # XHCI
device pci 15.0 on end # LPE
device pci 17.0 on end # MMC
device pci 18.0 on end # SIO_DMA1
device pci 18.1 on end # I2C1
device pci 18.2 on end # I2C2
device pci 18.3 off end # I2C3
device pci 18.4 off end # I2C4
device pci 18.5 off end # I2C5
device pci 18.6 off end # I2C6
device pci 18.7 off end # I2C7
device pci 1a.0 off end # TXE
device pci 1b.0 on end # HDA
device pci 1c.0 on end # PCIE_PORT1
device pci 1c.1 on end # PCIE_PORT2
device pci 1c.2 off end # PCIE_PORT3
device pci 1c.3 off end # PCIE_PORT4
device pci 1d.0 on end # EHCI
device pci 1e.0 on end # SIO_DMA2
device pci 1e.1 off end # PWM1
device pci 1e.2 off end # PWM2
device pci 1e.3 off end # HSUART1
device pci 1e.4 off end # HSUART2
device pci 1e.5 off end # SPI
device pci 1f.0 on
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
chip ec/google/chromeec
# We only have one init function that
# we need to call to initialize the
# keyboard part of the EC.
device pnp ff.1 on # dummy address
end
end
end # LPC Bridge
device pci 1f.3 off end # SMBus
end
end

9
src/mainboard/google/rambi/variants/enguarde/overridetree.cb Normal file
View File

@ -0,0 +1,9 @@
chip soc/intel/baytrail
# Allow PCIe devices to wake system from suspend
register "pcie_wake_enable" = "1"
device domain 0 on
device pci 1c.1 on end # PCIE_PORT2
end
end

101
src/mainboard/google/rambi/variants/glimmer/devicetree.cb
View File

@ -1,101 +0,0 @@
chip soc/intel/baytrail
# SATA port enable mask (2 ports)
register "sata_port_map" = "0x1"
register "sata_ahci" = "0x1"
register "ide_legacy_combined" = "0x0"
# Route USB ports to XHCI
register "usb_route_to_xhci" = "1"
# USB Port Disable Mask
register "usb2_port_disable_mask" = "0x0"
register "usb3_port_disable_mask" = "0x0"
# USB PHY settings
# TODO: These values are from Baytrail and need tuned for Glimmer board
register "usb2_per_port_lane0" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
register "usb2_per_port_lane1" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
register "usb2_per_port_lane2" = "0x00049209"
register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
register "usb2_per_port_lane3" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
# LPE audio codec settings
register "lpe_codec_clk_freq" = "25" # 25MHz clock
register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
# SD Card controller
register "sdcard_cap_low" = "0x036864b2"
register "sdcard_cap_high" = "0x0"
# Enable devices in ACPI mode
register "lpe_acpi_mode" = "1"
register "lpss_acpi_mode" = "1"
register "scc_acpi_mode" = "1"
# Enable PIPEA as DP_C
register "gpu_pipea_port_select" = "2" # DP_C
register "gpu_pipea_power_cycle_delay" = "6" # 600ms
register "gpu_pipea_power_on_delay" = "5000" # 500ms
register "gpu_pipea_light_on_delay" = "70" # 7ms
register "gpu_pipea_power_off_delay" = "500" # 50ms
register "gpu_pipea_light_off_delay" = "2000" # 200ms
# VR PS2 control
register "vnn_ps2_enable" = "1"
register "vcc_ps2_enable" = "1"
# Disable SLP_X stretching after SUS power well fail.
register "disable_slp_x_stretch_sus_fail" = "1"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # SoC router
device pci 02.0 on end # GFX
device pci 11.0 off end # SDIO
device pci 12.0 on end # SD
device pci 13.0 on end # SATA
device pci 14.0 on end # XHCI
device pci 15.0 on end # LPE
device pci 17.0 on end # MMC
device pci 18.0 on end # SIO_DMA1
device pci 18.1 on end # I2C1
device pci 18.2 on end # I2C2
device pci 18.3 off end # I2C3
device pci 18.4 off end # I2C4
device pci 18.5 off end # I2C5
device pci 18.6 on end # I2C6
device pci 18.7 off end # I2C7
device pci 1a.0 off end # TXE
device pci 1b.0 on end # HDA
device pci 1c.0 on end # PCIE_PORT1
device pci 1c.1 on end # PCIE_PORT2
device pci 1c.2 off end # PCIE_PORT3
device pci 1c.3 off end # PCIE_PORT4
device pci 1d.0 on end # EHCI
device pci 1e.0 on end # SIO_DMA2
device pci 1e.1 off end # PWM1
device pci 1e.2 off end # PWM2
device pci 1e.3 off end # HSUART1
device pci 1e.4 off end # HSUART2
device pci 1e.5 off end # SPI
device pci 1f.0 on
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
chip ec/google/chromeec
# We only have one init function that
# we need to call to initialize the
# keyboard part of the EC.
device pnp ff.1 on # dummy address
end
end
end # LPC Bridge
device pci 1f.3 off end # SMBus
end
end

7
src/mainboard/google/rambi/variants/glimmer/overridetree.cb Normal file
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chip soc/intel/baytrail
device domain 0 on
device pci 18.6 on end # I2C6
device pci 1c.1 on end # PCIE_PORT2
end
end

104
src/mainboard/google/rambi/variants/gnawty/devicetree.cb
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chip soc/intel/baytrail
# SATA port enable mask (2 ports)
register "sata_port_map" = "0x1"
register "sata_ahci" = "0x1"
register "ide_legacy_combined" = "0x0"
# Route USB ports to XHCI
register "usb_route_to_xhci" = "1"
# USB Port Disable Mask
register "usb2_port_disable_mask" = "0x0"
register "usb3_port_disable_mask" = "0x0"
# USB PHY settings
# TODO: These values are from Baytrail and need tuned for Gnawty board
register "usb2_per_port_lane0" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
register "usb2_per_port_lane1" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
register "usb2_per_port_lane2" = "0x00049209"
register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
register "usb2_per_port_lane3" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
# LPE audio codec settings
register "lpe_codec_clk_freq" = "25" # 25MHz clock
register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
# SD Card controller
register "sdcard_cap_low" = "0x036864b2"
register "sdcard_cap_high" = "0x0"
# Enable devices in ACPI mode
register "lpe_acpi_mode" = "1"
register "lpss_acpi_mode" = "1"
register "scc_acpi_mode" = "1"
# Allow PCIe devices to wake system from suspend
register "pcie_wake_enable" = "1"
# Enable PIPEA as DP_C
register "gpu_pipea_port_select" = "2" # DP_C
register "gpu_pipea_power_cycle_delay" = "6" # 600ms
register "gpu_pipea_power_on_delay" = "5000" # 500ms
register "gpu_pipea_light_on_delay" = "70" # 7ms
register "gpu_pipea_power_off_delay" = "500" # 50ms
register "gpu_pipea_light_off_delay" = "2000" # 200ms
# VR PS2 control
register "vnn_ps2_enable" = "1"
register "vcc_ps2_enable" = "1"
# Disable SLP_X stretching after SUS power well fail.
register "disable_slp_x_stretch_sus_fail" = "1"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # SoC router
device pci 02.0 on end # GFX
device pci 11.0 off end # SDIO
device pci 12.0 on end # SD
device pci 13.0 on end # SATA
device pci 14.0 on end # XHCI
device pci 15.0 on end # LPE
device pci 17.0 on end # MMC
device pci 18.0 on end # SIO_DMA1
device pci 18.1 on end # I2C1
device pci 18.2 on end # I2C2
device pci 18.3 off end # I2C3
device pci 18.4 off end # I2C4
device pci 18.5 off end # I2C5
device pci 18.6 off end # I2C6
device pci 18.7 off end # I2C7
device pci 1a.0 off end # TXE
device pci 1b.0 on end # HDA
device pci 1c.0 on end # PCIE_PORT1
device pci 1c.1 on end # PCIE_PORT2
device pci 1c.2 off end # PCIE_PORT3
device pci 1c.3 off end # PCIE_PORT4
device pci 1d.0 on end # EHCI
device pci 1e.0 on end # SIO_DMA2
device pci 1e.1 off end # PWM1
device pci 1e.2 off end # PWM2
device pci 1e.3 off end # HSUART1
device pci 1e.4 off end # HSUART2
device pci 1e.5 off end # SPI
device pci 1f.0 on
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
chip ec/google/chromeec
# We only have one init function that
# we need to call to initialize the
# keyboard part of the EC.
device pnp ff.1 on # dummy address
end
end
end # LPC Bridge
device pci 1f.3 off end # SMBus
end
end

9
src/mainboard/google/rambi/variants/gnawty/overridetree.cb Normal file
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chip soc/intel/baytrail
# Allow PCIe devices to wake system from suspend
register "pcie_wake_enable" = "1"
device domain 0 on
device pci 1c.1 on end # PCIE_PORT2
end
end

105
src/mainboard/google/rambi/variants/heli/devicetree.cb
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chip soc/intel/baytrail
# SATA port enable mask (2 ports)
register "sata_port_map" = "0x1"
register "sata_ahci" = "0x1"
register "ide_legacy_combined" = "0x0"
# Route USB ports to XHCI
register "usb_route_to_xhci" = "1"
# USB Port Disable Mask
register "usb2_port_disable_mask" = "0x0"
register "usb3_port_disable_mask" = "0x0"
# USB PHY settings
# TODO: These values are from Baytrail and need tuned for Heli board
register "usb2_per_port_lane0" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
register "usb2_per_port_lane1" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
register "usb2_per_port_lane2" = "0x00049209"
register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
register "usb2_per_port_lane3" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
register "usb2_comp_bg" = "0x4700"
# LPE audio codec settings
register "lpe_codec_clk_freq" = "25" # 25MHz clock
register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
# SD Card controller
register "sdcard_cap_low" = "0x036864b2"
register "sdcard_cap_high" = "0x0"
# Enable devices in ACPI mode
register "lpe_acpi_mode" = "1"
register "lpss_acpi_mode" = "1"
register "scc_acpi_mode" = "1"
# Allow PCIe devices to wake system from suspend
register "pcie_wake_enable" = "1"
# Enable PIPEA as DP_C
register "gpu_pipea_port_select" = "2" # DP_C
register "gpu_pipea_power_cycle_delay" = "6" # 600ms
register "gpu_pipea_power_on_delay" = "5000" # 500ms
register "gpu_pipea_light_on_delay" = "70" # 7ms
register "gpu_pipea_power_off_delay" = "500" # 50ms
register "gpu_pipea_light_off_delay" = "2000" # 200ms
# VR PS2 control
register "vnn_ps2_enable" = "1"
register "vcc_ps2_enable" = "1"
# Disable SLP_X stretching after SUS power well fail.
register "disable_slp_x_stretch_sus_fail" = "1"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # SoC router
device pci 02.0 on end # GFX
device pci 11.0 off end # SDIO
device pci 12.0 on end # SD
device pci 13.0 on end # SATA
device pci 14.0 on end # XHCI
device pci 15.0 on end # LPE
device pci 17.0 on end # MMC
device pci 18.0 on end # SIO_DMA1
device pci 18.1 on end # I2C1
device pci 18.2 on end # I2C2
device pci 18.3 off end # I2C3
device pci 18.4 off end # I2C4
device pci 18.5 off end # I2C5
device pci 18.6 off end # I2C6
device pci 18.7 off end # I2C7
device pci 1a.0 off end # TXE
device pci 1b.0 on end # HDA
device pci 1c.0 on end # PCIE_PORT1
device pci 1c.1 on end # PCIE_PORT2
device pci 1c.2 off end # PCIE_PORT3
device pci 1c.3 off end # PCIE_PORT4
device pci 1d.0 on end # EHCI
device pci 1e.0 on end # SIO_DMA2
device pci 1e.1 off end # PWM1
device pci 1e.2 off end # PWM2
device pci 1e.3 off end # HSUART1
device pci 1e.4 off end # HSUART2
device pci 1e.5 off end # SPI
device pci 1f.0 on
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
chip ec/google/chromeec
# We only have one init function that
# we need to call to initialize the
# keyboard part of the EC.
device pnp ff.1 on # dummy address
end
end
end # LPC Bridge
device pci 1f.3 off end # SMBus
end
end

11
src/mainboard/google/rambi/variants/heli/overridetree.cb Normal file
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chip soc/intel/baytrail
register "usb2_comp_bg" = "0x4700"
# Allow PCIe devices to wake system from suspend
register "pcie_wake_enable" = "1"
device domain 0 on
device pci 1c.1 on end # PCIE_PORT2
end
end

104
src/mainboard/google/rambi/variants/kip/devicetree.cb
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chip soc/intel/baytrail
# SATA port enable mask (2 ports)
register "sata_port_map" = "0x1"
register "sata_ahci" = "0x1"
register "ide_legacy_combined" = "0x0"
# Route USB ports to XHCI
register "usb_route_to_xhci" = "1"
# USB Port Disable Mask
register "usb2_port_disable_mask" = "0x0"
register "usb3_port_disable_mask" = "0x0"
# USB PHY settings
# TODO: These values are from Baytrail and need tuned for Kip board
register "usb2_per_port_lane0" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
register "usb2_per_port_lane1" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
register "usb2_per_port_lane2" = "0x00049209"
register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
register "usb2_per_port_lane3" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
# LPE audio codec settings
register "lpe_codec_clk_freq" = "25" # 25MHz clock
register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
# SD Card controller
register "sdcard_cap_low" = "0x036864b2"
register "sdcard_cap_high" = "0x0"
# Enable devices in ACPI mode
register "lpe_acpi_mode" = "1"
register "lpss_acpi_mode" = "1"
register "scc_acpi_mode" = "1"
# Allow PCIe devices to wake system from suspend
register "pcie_wake_enable" = "1"
# Enable PIPEA as DP_C
register "gpu_pipea_port_select" = "2" # DP_C
register "gpu_pipea_power_cycle_delay" = "6" # 600ms
register "gpu_pipea_power_on_delay" = "5000" # 500ms
register "gpu_pipea_light_on_delay" = "70" # 7ms
register "gpu_pipea_power_off_delay" = "500" # 50ms
register "gpu_pipea_light_off_delay" = "2000" # 200ms
# VR PS2 control
register "vnn_ps2_enable" = "1"
register "vcc_ps2_enable" = "1"
# Disable SLP_X stretching after SUS power well fail.
register "disable_slp_x_stretch_sus_fail" = "1"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # SoC router
device pci 02.0 on end # GFX
device pci 11.0 off end # SDIO
device pci 12.0 on end # SD
device pci 13.0 on end # SATA
device pci 14.0 on end # XHCI
device pci 15.0 on end # LPE
device pci 17.0 on end # MMC
device pci 18.0 on end # SIO_DMA1
device pci 18.1 on end # I2C1
device pci 18.2 on end # I2C2
device pci 18.3 off end # I2C3
device pci 18.4 off end # I2C4
device pci 18.5 off end # I2C5
device pci 18.6 off end # I2C6
device pci 18.7 off end # I2C7
device pci 1a.0 off end # TXE
device pci 1b.0 on end # HDA
device pci 1c.0 on end # PCIE_PORT1
device pci 1c.1 on end # PCIE_PORT2
device pci 1c.2 off end # PCIE_PORT3
device pci 1c.3 off end # PCIE_PORT4
device pci 1d.0 on end # EHCI
device pci 1e.0 on end # SIO_DMA2
device pci 1e.1 off end # PWM1
device pci 1e.2 off end # PWM2
device pci 1e.3 off end # HSUART1
device pci 1e.4 off end # HSUART2
device pci 1e.5 off end # SPI
device pci 1f.0 on
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
chip ec/google/chromeec
# We only have one init function that
# we need to call to initialize the
# keyboard part of the EC.
device pnp ff.1 on # dummy address
end
end
end # LPC Bridge
device pci 1f.3 off end # SMBus
end
end

9
src/mainboard/google/rambi/variants/kip/overridetree.cb Normal file
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chip soc/intel/baytrail
# Allow PCIe devices to wake system from suspend
register "pcie_wake_enable" = "1"
device domain 0 on
device pci 1c.1 on end # PCIE_PORT2
end
end

105
src/mainboard/google/rambi/variants/ninja/devicetree.cb
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chip soc/intel/baytrail
# SATA port enable mask (2 ports)
register "sata_port_map" = "0x1"
register "sata_ahci" = "0x1"
register "ide_legacy_combined" = "0x0"
# Route USB ports to XHCI
register "usb_route_to_xhci" = "1"
# USB Port Disable Mask
register "usb2_port_disable_mask" = "0x0"
register "usb3_port_disable_mask" = "0x0"
# USB PHY settings
# TODO: These values are from Baytrail and need tuned for Ninja board
register "usb2_per_port_lane0" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
register "usb2_per_port_lane1" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
register "usb2_per_port_lane2" = "0x00049209"
register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
register "usb2_per_port_lane3" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
register "usb2_comp_bg" = "0x4700"
# LPE audio codec settings
register "lpe_codec_clk_freq" = "25" # 25MHz clock
register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
# SD Card controller
register "sdcard_cap_low" = "0x036864b2"
register "sdcard_cap_high" = "0x0"
# Enable devices in ACPI mode
register "lpe_acpi_mode" = "1"
register "lpss_acpi_mode" = "1"
register "scc_acpi_mode" = "1"
# Allow PCIe devices to wake system from suspend
register "pcie_wake_enable" = "1"
# Enable PIPEA as DP_C
register "gpu_pipea_port_select" = "2" # DP_C
register "gpu_pipea_power_cycle_delay" = "6" # 600ms
register "gpu_pipea_power_on_delay" = "5000" # 500ms
register "gpu_pipea_light_on_delay" = "70" # 7ms
register "gpu_pipea_power_off_delay" = "500" # 50ms
register "gpu_pipea_light_off_delay" = "2000" # 200ms
# VR PS2 control
register "vnn_ps2_enable" = "1"
register "vcc_ps2_enable" = "1"
# Disable SLP_X stretching after SUS power well fail.
register "disable_slp_x_stretch_sus_fail" = "1"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # SoC router
device pci 02.0 on end # GFX
device pci 11.0 off end # SDIO
device pci 12.0 on end # SD
device pci 13.0 on end # SATA
device pci 14.0 on end # XHCI
device pci 15.0 on end # LPE
device pci 17.0 on end # MMC
device pci 18.0 on end # SIO_DMA1
device pci 18.1 on end # I2C1
device pci 18.2 on end # I2C2
device pci 18.3 off end # I2C3
device pci 18.4 off end # I2C4
device pci 18.5 off end # I2C5
device pci 18.6 off end # I2C6
device pci 18.7 off end # I2C7
device pci 1a.0 off end # TXE
device pci 1b.0 on end # HDA
device pci 1c.0 on end # PCIE_PORT1
device pci 1c.1 off end # PCIE_PORT2
device pci 1c.2 on end # PCIE_PORT3
device pci 1c.3 on end # PCIE_PORT4
device pci 1d.0 on end # EHCI
device pci 1e.0 on end # SIO_DMA2
device pci 1e.1 off end # PWM1
device pci 1e.2 off end # PWM2
device pci 1e.3 off end # HSUART1
device pci 1e.4 off end # HSUART2
device pci 1e.5 off end # SPI
device pci 1f.0 on
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
chip ec/google/chromeec
# We only have one init function that
# we need to call to initialize the
# keyboard part of the EC.
device pnp ff.1 on # dummy address
end
end
end # LPC Bridge
device pci 1f.3 off end # SMBus
end
end

12
src/mainboard/google/rambi/variants/ninja/overridetree.cb Normal file
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chip soc/intel/baytrail
register "usb2_comp_bg" = "0x4700"
# Allow PCIe devices to wake system from suspend
register "pcie_wake_enable" = "1"
device domain 0 on
device pci 1c.2 on end # PCIE_PORT3
device pci 1c.3 on end # PCIE_PORT4
end
end

104
src/mainboard/google/rambi/variants/orco/devicetree.cb
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chip soc/intel/baytrail
# SATA port enable mask (2 ports)
register "sata_port_map" = "0x1"
register "sata_ahci" = "0x1"
register "ide_legacy_combined" = "0x0"
# Route USB ports to XHCI
register "usb_route_to_xhci" = "1"
# USB Port Disable Mask
register "usb2_port_disable_mask" = "0x0"
register "usb3_port_disable_mask" = "0x0"
# USB PHY settings
# TODO: These values are from Baytrail and need tuned for Orco board
register "usb2_per_port_lane0" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
register "usb2_per_port_lane1" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
register "usb2_per_port_lane2" = "0x00049209"
register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
register "usb2_per_port_lane3" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
# LPE audio codec settings
register "lpe_codec_clk_freq" = "25" # 25MHz clock
register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
# SD Card controller
register "sdcard_cap_low" = "0x036864b2"
register "sdcard_cap_high" = "0x0"
# Enable devices in ACPI mode
register "lpe_acpi_mode" = "1"
register "lpss_acpi_mode" = "1"
register "scc_acpi_mode" = "1"
# Allow PCIe devices to wake system from suspend
register "pcie_wake_enable" = "1"
# Enable PIPEA as DP_C
register "gpu_pipea_port_select" = "2" # DP_C
register "gpu_pipea_power_cycle_delay" = "6" # 600ms
register "gpu_pipea_power_on_delay" = "5000" # 500ms
register "gpu_pipea_light_on_delay" = "70" # 7ms
register "gpu_pipea_power_off_delay" = "500" # 50ms
register "gpu_pipea_light_off_delay" = "2000" # 200ms
# VR PS2 control
register "vnn_ps2_enable" = "1"
register "vcc_ps2_enable" = "1"
# Disable SLP_X stretching after SUS power well fail.
register "disable_slp_x_stretch_sus_fail" = "1"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # SoC router
device pci 02.0 on end # GFX
device pci 11.0 off end # SDIO
device pci 12.0 on end # SD
device pci 13.0 on end # SATA
device pci 14.0 on end # XHCI
device pci 15.0 on end # LPE
device pci 17.0 on end # MMC
device pci 18.0 on end # SIO_DMA1
device pci 18.1 on end # I2C1
device pci 18.2 on end # I2C2
device pci 18.3 off end # I2C3
device pci 18.4 off end # I2C4
device pci 18.5 off end # I2C5
device pci 18.6 off end # I2C6
device pci 18.7 off end # I2C7
device pci 1a.0 off end # TXE
device pci 1b.0 on end # HDA
device pci 1c.0 on end # PCIE_PORT1
device pci 1c.1 on end # PCIE_PORT2
device pci 1c.2 off end # PCIE_PORT3
device pci 1c.3 off end # PCIE_PORT4
device pci 1d.0 on end # EHCI
device pci 1e.0 on end # SIO_DMA2
device pci 1e.1 off end # PWM1
device pci 1e.2 off end # PWM2
device pci 1e.3 off end # HSUART1
device pci 1e.4 off end # HSUART2
device pci 1e.5 off end # SPI
device pci 1f.0 on
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
chip ec/google/chromeec
# We only have one init function that
# we need to call to initialize the
# keyboard part of the EC.
device pnp ff.1 on # dummy address
end
end
end # LPC Bridge
device pci 1f.3 off end # SMBus
end
end

9
src/mainboard/google/rambi/variants/orco/overridetree.cb Normal file
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chip soc/intel/baytrail
# Allow PCIe devices to wake system from suspend
register "pcie_wake_enable" = "1"
device domain 0 on
device pci 1c.1 on end # PCIE_PORT2
end
end

6
src/mainboard/google/rambi/variants/quawks/overridetree.cb Normal file
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chip soc/intel/baytrail
device domain 0 on
device pci 1c.1 on end # PCIE_PORT2
end
end

105
src/mainboard/google/rambi/variants/rambi/devicetree.cb
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chip soc/intel/baytrail
# SATA port enable mask (2 ports)
register "sata_port_map" = "0x1"
register "sata_ahci" = "0x1"
register "ide_legacy_combined" = "0x0"
# Route USB ports to XHCI
register "usb_route_to_xhci" = "1"
# USB Port Disable Mask
register "usb2_port_disable_mask" = "0x0"
register "usb3_port_disable_mask" = "0x0"
# USB PHY settings
# TODO: These values are from Baytrail and need tuned for Rambi board
register "usb2_per_port_lane0" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
register "usb2_per_port_lane1" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
register "usb2_per_port_lane2" = "0x00049209"
register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
register "usb2_per_port_lane3" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
register "usb2_comp_bg" = "0x4700"
# LPE audio codec settings
register "lpe_codec_clk_freq" = "25" # 25MHz clock
register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
# SD Card controller
register "sdcard_cap_low" = "0x036864b2"
register "sdcard_cap_high" = "0x0"
# Enable devices in ACPI mode
register "lpe_acpi_mode" = "1"
register "lpss_acpi_mode" = "1"
register "scc_acpi_mode" = "1"
# Allow PCIe devices to wake system from suspend
register "pcie_wake_enable" = "1"
# Enable PIPEA as DP_C
register "gpu_pipea_port_select" = "2" # DP_C
register "gpu_pipea_power_cycle_delay" = "6" # 600ms
register "gpu_pipea_power_on_delay" = "5000" # 500ms
register "gpu_pipea_light_on_delay" = "70" # 7ms
register "gpu_pipea_power_off_delay" = "500" # 50ms
register "gpu_pipea_light_off_delay" = "2000" # 200ms
# VR PS2 control
register "vnn_ps2_enable" = "1"
register "vcc_ps2_enable" = "1"
# Disable SLP_X stretching after SUS power well fail.
register "disable_slp_x_stretch_sus_fail" = "1"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # SoC router
device pci 02.0 on end # GFX
device pci 11.0 off end # SDIO
device pci 12.0 on end # SD
device pci 13.0 on end # SATA
device pci 14.0 on end # XHCI
device pci 15.0 on end # LPE
device pci 17.0 on end # MMC
device pci 18.0 on end # SIO_DMA1
device pci 18.1 on end # I2C1
device pci 18.2 on end # I2C2
device pci 18.3 off end # I2C3
device pci 18.4 off end # I2C4
device pci 18.5 off end # I2C5
device pci 18.6 on end # I2C6
device pci 18.7 off end # I2C7
device pci 1a.0 off end # TXE
device pci 1b.0 on end # HDA
device pci 1c.0 on end # PCIE_PORT1
device pci 1c.1 on end # PCIE_PORT2
device pci 1c.2 off end # PCIE_PORT3
device pci 1c.3 off end # PCIE_PORT4
device pci 1d.0 on end # EHCI
device pci 1e.0 on end # SIO_DMA2
device pci 1e.1 off end # PWM1
device pci 1e.2 off end # PWM2
device pci 1e.3 off end # HSUART1
device pci 1e.4 off end # HSUART2
device pci 1e.5 off end # SPI
device pci 1f.0 on
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
chip ec/google/chromeec
# We only have one init function that
# we need to call to initialize the
# keyboard part of the EC.
device pnp ff.1 on # dummy address
end
end
end # LPC Bridge
device pci 1f.3 off end # SMBus
end
end

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src/mainboard/google/rambi/variants/rambi/overridetree.cb Normal file
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chip soc/intel/baytrail
register "usb2_comp_bg" = "0x4700"
# Allow PCIe devices to wake system from suspend
register "pcie_wake_enable" = "1"
device domain 0 on
device pci 18.6 on end # I2C6
device pci 1c.1 on end # PCIE_PORT2
end
end

101
src/mainboard/google/rambi/variants/squawks/devicetree.cb
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chip soc/intel/baytrail
# SATA port enable mask (2 ports)
register "sata_port_map" = "0x1"
register "sata_ahci" = "0x1"
register "ide_legacy_combined" = "0x0"
# Route USB ports to XHCI
register "usb_route_to_xhci" = "1"
# USB Port Disable Mask
register "usb2_port_disable_mask" = "0x0"
register "usb3_port_disable_mask" = "0x0"
# USB PHY settings
# TODO: These values are from Baytrail and need tuned for Squawks board
register "usb2_per_port_lane0" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
register "usb2_per_port_lane1" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
register "usb2_per_port_lane2" = "0x00049209"
register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
register "usb2_per_port_lane3" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
# LPE audio codec settings
register "lpe_codec_clk_freq" = "25" # 25MHz clock
register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
# SD Card controller
register "sdcard_cap_low" = "0x036864b2"
register "sdcard_cap_high" = "0x0"
# Enable devices in ACPI mode
register "lpe_acpi_mode" = "1"
register "lpss_acpi_mode" = "1"
register "scc_acpi_mode" = "1"
# Enable PIPEA as DP_C
register "gpu_pipea_port_select" = "2" # DP_C
register "gpu_pipea_power_cycle_delay" = "6" # 600ms
register "gpu_pipea_power_on_delay" = "5000" # 500ms
register "gpu_pipea_light_on_delay" = "70" # 7ms
register "gpu_pipea_power_off_delay" = "500" # 50ms
register "gpu_pipea_light_off_delay" = "2000" # 200ms
# VR PS2 control
register "vnn_ps2_enable" = "1"
register "vcc_ps2_enable" = "1"
# Disable SLP_X stretching after SUS power well fail.
register "disable_slp_x_stretch_sus_fail" = "1"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # SoC router
device pci 02.0 on end # GFX
device pci 11.0 off end # SDIO
device pci 12.0 on end # SD
device pci 13.0 on end # SATA
device pci 14.0 on end # XHCI
device pci 15.0 on end # LPE
device pci 17.0 on end # MMC
device pci 18.0 on end # SIO_DMA1
device pci 18.1 on end # I2C1
device pci 18.2 on end # I2C2
device pci 18.3 off end # I2C3
device pci 18.4 off end # I2C4
device pci 18.5 off end # I2C5
device pci 18.6 off end # I2C6
device pci 18.7 off end # I2C7
device pci 1a.0 off end # TXE
device pci 1b.0 on end # HDA
device pci 1c.0 on end # PCIE_PORT1
device pci 1c.1 on end # PCIE_PORT2
device pci 1c.2 off end # PCIE_PORT3
device pci 1c.3 off end # PCIE_PORT4
device pci 1d.0 on end # EHCI
device pci 1e.0 on end # SIO_DMA2
device pci 1e.1 off end # PWM1
device pci 1e.2 off end # PWM2
device pci 1e.3 off end # HSUART1
device pci 1e.4 off end # HSUART2
device pci 1e.5 off end # SPI
device pci 1f.0 on
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
chip ec/google/chromeec
# We only have one init function that
# we need to call to initialize the
# keyboard part of the EC.
device pnp ff.1 on # dummy address
end
end
end # LPC Bridge
device pci 1f.3 off end # SMBus
end
end

6
src/mainboard/google/rambi/variants/squawks/overridetree.cb Normal file
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chip soc/intel/baytrail
device domain 0 on
device pci 1c.1 on end # PCIE_PORT2
end
end

105
src/mainboard/google/rambi/variants/sumo/devicetree.cb
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chip soc/intel/baytrail
# SATA port enable mask (2 ports)
register "sata_port_map" = "0x1"
register "sata_ahci" = "0x1"
register "ide_legacy_combined" = "0x0"
# Route USB ports to XHCI
register "usb_route_to_xhci" = "1"
# USB Port Disable Mask
register "usb2_port_disable_mask" = "0x0"
register "usb3_port_disable_mask" = "0x0"
# USB PHY settings
# TODO: These values are from Baytrail and need tuned for Sumo board
register "usb2_per_port_lane0" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
register "usb2_per_port_lane1" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
register "usb2_per_port_lane2" = "0x00049209"
register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
register "usb2_per_port_lane3" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
register "usb2_comp_bg" = "0x4700"
# LPE audio codec settings
register "lpe_codec_clk_freq" = "25" # 25MHz clock
register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
# SD Card controller
register "sdcard_cap_low" = "0x036864b2"
register "sdcard_cap_high" = "0x0"
# Enable devices in ACPI mode
register "lpe_acpi_mode" = "1"
register "lpss_acpi_mode" = "1"
register "scc_acpi_mode" = "1"
# Allow PCIe devices to wake system from suspend
register "pcie_wake_enable" = "1"
# Enable PIPEA as DP_C
register "gpu_pipea_port_select" = "2" # DP_C
register "gpu_pipea_power_cycle_delay" = "6" # 600ms
register "gpu_pipea_power_on_delay" = "5000" # 500ms
register "gpu_pipea_light_on_delay" = "70" # 7ms
register "gpu_pipea_power_off_delay" = "500" # 50ms
register "gpu_pipea_light_off_delay" = "2000" # 200ms
# VR PS2 control
register "vnn_ps2_enable" = "1"
register "vcc_ps2_enable" = "1"
# Disable SLP_X stretching after SUS power well fail.
register "disable_slp_x_stretch_sus_fail" = "1"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # SoC router
device pci 02.0 on end # GFX
device pci 11.0 off end # SDIO
device pci 12.0 on end # SD
device pci 13.0 on end # SATA
device pci 14.0 on end # XHCI
device pci 15.0 on end # LPE
device pci 17.0 on end # MMC
device pci 18.0 on end # SIO_DMA1
device pci 18.1 on end # I2C1
device pci 18.2 on end # I2C2
device pci 18.3 off end # I2C3
device pci 18.4 off end # I2C4
device pci 18.5 off end # I2C5
device pci 18.6 on end # I2C6
device pci 18.7 off end # I2C7
device pci 1a.0 off end # TXE
device pci 1b.0 on end # HDA
device pci 1c.0 on end # PCIE_PORT1
device pci 1c.1 off end # PCIE_PORT2
device pci 1c.2 on end # PCIE_PORT3
device pci 1c.3 on end # PCIE_PORT4
device pci 1d.0 on end # EHCI
device pci 1e.0 on end # SIO_DMA2
device pci 1e.1 off end # PWM1
device pci 1e.2 off end # PWM2
device pci 1e.3 off end # HSUART1
device pci 1e.4 off end # HSUART2
device pci 1e.5 off end # SPI
device pci 1f.0 on
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
chip ec/google/chromeec
# We only have one init function that
# we need to call to initialize the
# keyboard part of the EC.
device pnp ff.1 on # dummy address
end
end
end # LPC Bridge
device pci 1f.3 off end # SMBus
end
end

13
src/mainboard/google/rambi/variants/sumo/overridetree.cb Normal file
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chip soc/intel/baytrail
register "usb2_comp_bg" = "0x4700"
# Allow PCIe devices to wake system from suspend
register "pcie_wake_enable" = "1"
device domain 0 on
device pci 18.6 on end # I2C6
device pci 1c.2 on end # PCIE_PORT3
device pci 1c.3 on end # PCIE_PORT4
end
end

104
src/mainboard/google/rambi/variants/swanky/devicetree.cb
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chip soc/intel/baytrail
# SATA port enable mask (2 ports)
register "sata_port_map" = "0x1"
register "sata_ahci" = "0x1"
register "ide_legacy_combined" = "0x0"
# Route USB ports to XHCI
register "usb_route_to_xhci" = "1"
# USB Port Disable Mask
register "usb2_port_disable_mask" = "0x0"
register "usb3_port_disable_mask" = "0x0"
# USB PHY settings
# TODO: These values are from Baytrail and need tuned for Swanky board
register "usb2_per_port_lane0" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
register "usb2_per_port_lane1" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
register "usb2_per_port_lane2" = "0x00049209"
register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
register "usb2_per_port_lane3" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
# LPE audio codec settings
register "lpe_codec_clk_freq" = "25" # 25MHz clock
register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
# SD Card controller
register "sdcard_cap_low" = "0x036864b2"
register "sdcard_cap_high" = "0x0"
# Enable devices in ACPI mode
register "lpe_acpi_mode" = "1"
register "lpss_acpi_mode" = "1"
register "scc_acpi_mode" = "1"
# Allow PCIe devices to wake system from suspend
register "pcie_wake_enable" = "1"
# Enable PIPEA as DP_C
register "gpu_pipea_port_select" = "2" # DP_C
register "gpu_pipea_power_cycle_delay" = "6" # 600ms
register "gpu_pipea_power_on_delay" = "5000" # 500ms
register "gpu_pipea_light_on_delay" = "70" # 7ms
register "gpu_pipea_power_off_delay" = "500" # 50ms
register "gpu_pipea_light_off_delay" = "2000" # 200ms
# VR PS2 control
register "vnn_ps2_enable" = "1"
register "vcc_ps2_enable" = "1"
# Disable SLP_X stretching after SUS power well fail.
register "disable_slp_x_stretch_sus_fail" = "1"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # SoC router
device pci 02.0 on end # GFX
device pci 11.0 off end # SDIO
device pci 12.0 on end # SD
device pci 13.0 on end # SATA
device pci 14.0 on end # XHCI
device pci 15.0 on end # LPE
device pci 17.0 on end # MMC
device pci 18.0 on end # SIO_DMA1
device pci 18.1 on end # I2C1
device pci 18.2 on end # I2C2
device pci 18.3 off end # I2C3
device pci 18.4 off end # I2C4
device pci 18.5 off end # I2C5
device pci 18.6 off end # I2C6
device pci 18.7 off end # I2C7
device pci 1a.0 off end # TXE
device pci 1b.0 on end # HDA
device pci 1c.0 on end # PCIE_PORT1
device pci 1c.1 on end # PCIE_PORT2
device pci 1c.2 off end # PCIE_PORT3
device pci 1c.3 off end # PCIE_PORT4
device pci 1d.0 on end # EHCI
device pci 1e.0 on end # SIO_DMA2
device pci 1e.1 off end # PWM1
device pci 1e.2 off end # PWM2
device pci 1e.3 off end # HSUART1
device pci 1e.4 off end # HSUART2
device pci 1e.5 off end # SPI
device pci 1f.0 on
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
chip ec/google/chromeec
# We only have one init function that
# we need to call to initialize the
# keyboard part of the EC.
device pnp ff.1 on # dummy address
end
end
end # LPC Bridge
device pci 1f.3 off end # SMBus
end
end

9
src/mainboard/google/rambi/variants/swanky/overridetree.cb Normal file
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chip soc/intel/baytrail
# Allow PCIe devices to wake system from suspend
register "pcie_wake_enable" = "1"
device domain 0 on
device pci 1c.1 on end # PCIE_PORT2
end
end

105
src/mainboard/google/rambi/variants/winky/devicetree.cb
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chip soc/intel/baytrail
# SATA port enable mask (2 ports)
register "sata_port_map" = "0x1"
register "sata_ahci" = "0x1"
register "ide_legacy_combined" = "0x0"
# Route USB ports to XHCI
register "usb_route_to_xhci" = "1"
# USB Port Disable Mask
register "usb2_port_disable_mask" = "0x0"
register "usb3_port_disable_mask" = "0x0"
# USB PHY settings
# TODO: These values are from Baytrail and need tuned for Winky board
register "usb2_comp_bg" = "0x4680"
register "usb2_per_port_lane0" = "0x0004C209"
register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
register "usb2_per_port_lane1" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
register "usb2_per_port_lane2" = "0x00049209"
register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
register "usb2_per_port_lane3" = "0x0004B209"
register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
# LPE audio codec settings
register "lpe_codec_clk_freq" = "25" # 25MHz clock
register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
# SD Card controller
register "sdcard_cap_low" = "0x036864b2"
register "sdcard_cap_high" = "0x0"
# Enable devices in ACPI mode
register "lpe_acpi_mode" = "1"
register "lpss_acpi_mode" = "1"
register "scc_acpi_mode" = "1"
# Allow PCIe devices to wake system from suspend
register "pcie_wake_enable" = "1"
# Enable PIPEA as DP_C
register "gpu_pipea_port_select" = "2" # DP_C
register "gpu_pipea_power_cycle_delay" = "6" # 600ms
register "gpu_pipea_power_on_delay" = "5000" # 500ms
register "gpu_pipea_light_on_delay" = "70" # 7ms
register "gpu_pipea_power_off_delay" = "500" # 50ms
register "gpu_pipea_light_off_delay" = "2000" # 200ms
# VR PS2 control
register "vnn_ps2_enable" = "1"
register "vcc_ps2_enable" = "1"
# Disable SLP_X stretching after SUS power well fail.
register "disable_slp_x_stretch_sus_fail" = "1"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # SoC router
device pci 02.0 on end # GFX
device pci 11.0 off end # SDIO
device pci 12.0 on end # SD
device pci 13.0 on end # SATA
device pci 14.0 on end # XHCI
device pci 15.0 on end # LPE
device pci 17.0 on end # MMC
device pci 18.0 on end # SIO_DMA1
device pci 18.1 on end # I2C1
device pci 18.2 on end # I2C2
device pci 18.3 off end # I2C3
device pci 18.4 off end # I2C4
device pci 18.5 off end # I2C5
device pci 18.6 off end # I2C6
device pci 18.7 off end # I2C7
device pci 1a.0 off end # TXE
device pci 1b.0 on end # HDA
device pci 1c.0 on end # PCIE_PORT1
device pci 1c.1 on end # PCIE_PORT2
device pci 1c.2 off end # PCIE_PORT3
device pci 1c.3 off end # PCIE_PORT4
device pci 1d.0 on end # EHCI
device pci 1e.0 on end # SIO_DMA2
device pci 1e.1 off end # PWM1
device pci 1e.2 off end # PWM2
device pci 1e.3 off end # HSUART1
device pci 1e.4 off end # HSUART2
device pci 1e.5 off end # SPI
device pci 1f.0 on
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
chip ec/google/chromeec
# We only have one init function that
# we need to call to initialize the
# keyboard part of the EC.
device pnp ff.1 on # dummy address
end
end
end # LPC Bridge
device pci 1f.3 off end # SMBus
end
end

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src/mainboard/google/rambi/variants/winky/overridetree.cb Normal file
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chip soc/intel/baytrail
register "usb2_per_port_lane0" = "0x0004C209"
register "usb2_per_port_lane3" = "0x0004B209"
register "usb2_comp_bg" = "0x4680"
# Allow PCIe devices to wake system from suspend
register "pcie_wake_enable" = "1"
device domain 0 on
device pci 1c.1 on end # PCIE_PORT2
end
end