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mb/google/volteer/halvor: Update settings for WiFi/BT functions 

Configure gpio/overridetree settings for WiFi/BT functions.
Then WiFi/BT functions are enabled on Halvor.

BUG=b:153680359, b:163004808
TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage
Verify that WiFi/BT can scan devices successfully.

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I085b192bb768c2c1238f3f857d315502ac10857e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44372
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Frank Wu 2020-08-11 16:04:45 +08:00 committed by Tim Wawrzynczak
parent e915cfc0d8
commit 1d7ba15aa2
2 changed files with 5 additions and 1 deletions
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4
src/mainboard/google/volteer/variants/halvor/gpio.c
View File

@ -23,6 +23,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
/* A10 : I2S2_RXD ==> I2S1_RXD */
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
PAD_CFG_GPO(GPP_A13, 1, DEEP),
/* A18 : DDSP_HPDB ==> NC */
PAD_NC(GPP_A18, NONE),
/* A22 : DDPC_CTRLDATA ==> NC */
@ -96,6 +98,8 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_F11, NONE),
/* F12 : GSXDOUT ==> EN_PP3300_TRACKPAD */
PAD_CFG_GPO(GPP_F12, 1, DEEP),
/* F13 : GSXDOUT ==> WiFi_DISABLE_L */
PAD_CFG_GPO(GPP_F13, 1, DEEP),
/* F14 : GSXDIN ==> NC */
PAD_NC(GPP_F14, NONE),
/* F15 : GSXSRESET# ==> NC */

2
src/mainboard/google/volteer/variants/halvor/overridetree.cb
View File

@ -8,7 +8,7 @@ chip soc/intel/tigerlake
register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Reserve for CNVi BT
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A / Type-C Port 1