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Prepare for next patches (Improving BKDG implementation of P-states, 

CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode).

No change of behaviour intended.

Refactor FAM10 fidvid . prep_fid_change was already long and it'd
get longer with forthcoming patches. We now take apart F3xDC[NbsynPtrAdj],
Northbridge/core synchronization FIFO pointer adjust, to its own function.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6390 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Xavi Drudis Ferran 2011-02-27 23:50:30 +00:00 committed by Marc Jones
parent 9683b1deb2
commit 1d80e51017
1 changed files with 13 additions and 7 deletions
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20
src/cpu/amd/model_10xxx/fidvid.c
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@ -258,6 +258,17 @@ static void config_power_ctrl_misc_reg(device_t dev) {
} }
} }
static void config_nb_syn_ptr_adj(device_t dev) {
/* Note the following settings are additional from the ported
* function setFidVidRegs()
*/
u32 dword = pci_read_config32(dev, 0xDc);
dword |= 0x5 << 12; /* NbsynPtrAdj set to 0x5 per BKDG (needs reset) */
pci_write_config32(dev, 0xdc, dword);
}
static void prep_fid_change(void) static void prep_fid_change(void)
{ {
u32 dword; u32 dword;
@ -281,13 +292,8 @@ static void prep_fid_change(void)
config_clk_power_ctrl_reg0(i); config_clk_power_ctrl_reg0(i);
config_power_ctrl_misc_reg(dev); config_power_ctrl_misc_reg(dev);
/* Note the following settings are additional from the ported config_nb_syn_ptr_adj(dev);
* function setFidVidRegs()
*/
dword = pci_read_config32(dev, 0xDc);
dword |= 0x5 << 12; /* NbsynPtrAdj set to 0x5 per BKDG (needs reset) */
pci_write_config32(dev, 0xdc, dword);
/* Rev B settings - FIXME: support other revs. */ /* Rev B settings - FIXME: support other revs. */
dword = 0xA0E641E6; dword = 0xA0E641E6;