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some ifdef --> if fixes 

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2011-04-21 20:24:43 +00:00 committed by Stefan Reinauer
parent 305f2f50ab
commit 1d888a9784
18 changed files with 68 additions and 59 deletions
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10
src/Kconfig.deprecated_options
View File

@ -51,4 +51,14 @@ config DRIVERS_PS2_KEYBOARD
this option, then you can say N here to speed up boot time. this option, then you can say N here to speed up boot time.
Otherwise say Y. Otherwise say Y.
# This was a config option for a long time, but it never showed up in Kconfig.
# It should go away and "tuning" should always be enabled when PCIe is there,
# or it should be more fine grained (ie. Enable PCIe ASPM)
config PCIE_TUNING
bool
default n
help
This variable enables certain PCIe optimizations. Right now it's
only ASPM and it's untested.
endmenu endmenu

2
src/arch/x86/boot/coreboot_table.c
View File

@ -145,7 +145,7 @@ static void lb_console(struct lb_header *header)
static void lb_framebuffer(struct lb_header *header) static void lb_framebuffer(struct lb_header *header)
{ {
#if defined(CONFIG_BOOTSPLASH) && CONFIG_BOOTSPLASH && CONFIG_COREBOOT_KEEP_FRAMEBUFFER #if CONFIG_BOOTSPLASH && CONFIG_COREBOOT_KEEP_FRAMEBUFFER
void fill_lb_framebuffer(struct lb_framebuffer *framebuffer); void fill_lb_framebuffer(struct lb_framebuffer *framebuffer);
struct lb_framebuffer *framebuffer; struct lb_framebuffer *framebuffer;

2
src/arch/x86/include/arch/interrupt.h
View File

@ -22,7 +22,7 @@
#include "registers.h" #include "registers.h"
/* setup interrupt handlers for mainboard */ /* setup interrupt handlers for mainboard */
#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE #if CONFIG_PCI_OPTION_ROM_RUN_REALMODE
extern void mainboard_interrupt_handlers(int intXX, void *intXX_func); extern void mainboard_interrupt_handlers(int intXX, void *intXX_func);
#else #else
static inline void mainboard_interrupt_handlers(int intXX, void *intXX_func) { } static inline void mainboard_interrupt_handlers(int intXX, void *intXX_func) { }

18
src/devices/oprom/yabel/device.c
View File

@ -37,7 +37,7 @@ typedef struct {
u64 size; u64 size;
} __attribute__ ((__packed__)) assigned_address_t; } __attribute__ ((__packed__)) assigned_address_t;
#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL #if CONFIG_PCI_OPTION_ROM_RUN_YABEL
/* coreboot version */ /* coreboot version */
static void static void
@ -110,7 +110,7 @@ biosemu_dev_get_addr_info(void)
} }
// store last entry index of translate_address_array // store last entry index of translate_address_array
taa_last_entry = taa_index - 1; taa_last_entry = taa_index - 1;
#if defined(CONFIG_X86EMU_DEBUG) && CONFIG_X86EMU_DEBUG #if CONFIG_X86EMU_DEBUG
//dump translate_address_array //dump translate_address_array
printf("translate_address_array: \n"); printf("translate_address_array: \n");
translate_address_t ta; translate_address_t ta;
@ -194,7 +194,7 @@ biosemu_dev_get_addr_info(void)
} }
// store last entry index of translate_address_array // store last entry index of translate_address_array
taa_last_entry = taa_index - 1; taa_last_entry = taa_index - 1;
#if defined(CONFIG_X86EMU_DEBUG) && CONFIG_X86EMU_DEBUG #if CONFIG_X86EMU_DEBUG
//dump translate_address_array //dump translate_address_array
printf("translate_address_array: \n"); printf("translate_address_array: \n");
translate_address_t ta; translate_address_t ta;
@ -226,7 +226,7 @@ biosemu_add_special_memory(u32 start, u32 size)
translate_address_array[taa_index].address_offset = 0; translate_address_array[taa_index].address_offset = 0;
} }
#ifndef CONFIG_PCI_OPTION_ROM_RUN_YABEL #if !CONFIG_PCI_OPTION_ROM_RUN_YABEL
// to simulate accesses to legacy VGA Memory (0xA0000-0xBFFFF) // to simulate accesses to legacy VGA Memory (0xA0000-0xBFFFF)
// we look for the first prefetchable memory BAR, if no prefetchable BAR found, // we look for the first prefetchable memory BAR, if no prefetchable BAR found,
// we use the first memory BAR // we use the first memory BAR
@ -288,7 +288,7 @@ biosemu_dev_get_device_vendor_id(void)
{ {
u32 pci_config_0; u32 pci_config_0;
#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL #if CONFIG_PCI_OPTION_ROM_RUN_YABEL
pci_config_0 = pci_read_config32(bios_device.dev, 0x0); pci_config_0 = pci_read_config32(bios_device.dev, 0x0);
#else #else
pci_config_0 = pci_config_0 =
@ -350,7 +350,7 @@ biosemu_dev_check_exprom(unsigned long rom_base_addr)
memcpy(&pci_ds, (void *) (rom_base_addr + pci_ds_offset), memcpy(&pci_ds, (void *) (rom_base_addr + pci_ds_offset),
sizeof(pci_ds)); sizeof(pci_ds));
clr_ci(); clr_ci();
#if defined(CONFIG_X86EMU_DEBUG) && CONFIG_X86EMU_DEBUG #if CONFIG_X86EMU_DEBUG
DEBUG_PRINTF("PCI Data Structure @%lx:\n", DEBUG_PRINTF("PCI Data Structure @%lx:\n",
rom_base_addr + pci_ds_offset); rom_base_addr + pci_ds_offset);
dump((void *) &pci_ds, sizeof(pci_ds)); dump((void *) &pci_ds, sizeof(pci_ds));
@ -412,7 +412,7 @@ biosemu_dev_init(struct device * device)
DEBUG_PRINTF("%s\n", __func__); DEBUG_PRINTF("%s\n", __func__);
memset(&bios_device, 0, sizeof(bios_device)); memset(&bios_device, 0, sizeof(bios_device));
#ifndef CONFIG_PCI_OPTION_ROM_RUN_YABEL #if !CONFIG_PCI_OPTION_ROM_RUN_YABEL
bios_device.ihandle = of_open(device_name); bios_device.ihandle = of_open(device_name);
if (bios_device.ihandle == 0) { if (bios_device.ihandle == 0) {
DEBUG_PRINTF("%s is no valid device!\n", device_name); DEBUG_PRINTF("%s is no valid device!\n", device_name);
@ -423,7 +423,7 @@ biosemu_dev_init(struct device * device)
bios_device.dev = device; bios_device.dev = device;
#endif #endif
biosemu_dev_get_addr_info(); biosemu_dev_get_addr_info();
#ifndef CONFIG_PCI_OPTION_ROM_RUN_YABEL #if !CONFIG_PCI_OPTION_ROM_RUN_YABEL
biosemu_dev_find_vmem_addr(); biosemu_dev_find_vmem_addr();
biosemu_dev_get_puid(); biosemu_dev_get_puid();
#endif #endif
@ -440,7 +440,7 @@ biosemu_dev_translate_address(int type, unsigned long * addr)
{ {
int i = 0; int i = 0;
translate_address_t ta; translate_address_t ta;
#ifndef CONFIG_PCI_OPTION_ROM_RUN_YABEL #if !CONFIG_PCI_OPTION_ROM_RUN_YABEL
/* we dont need this hack for coreboot... we can access legacy areas */ /* we dont need this hack for coreboot... we can access legacy areas */
//check if it is an access to legacy VGA Mem... if it is, map the address //check if it is an access to legacy VGA Mem... if it is, map the address
//to the vmem BAR and then translate it... //to the vmem BAR and then translate it...

23
src/devices/oprom/yabel/interrupt.c
View File

@ -24,7 +24,7 @@
#include <x86emu/x86emu.h> #include <x86emu/x86emu.h>
#include "../x86emu/prim_ops.h" #include "../x86emu/prim_ops.h"
#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL #if CONFIG_PCI_OPTION_ROM_RUN_YABEL
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#endif #endif
@ -343,7 +343,7 @@ handleInt1a(void)
DEBUG_PRINTF_INTR("%s(): function: %x: PCI Find Device\n", DEBUG_PRINTF_INTR("%s(): function: %x: PCI Find Device\n",
__func__, M.x86.R_AX); __func__, M.x86.R_AX);
/* FixME: support SI != 0 */ /* FixME: support SI != 0 */
#if defined(CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES) && CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES==1 #if CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES
dev = dev_find_device(M.x86.R_DX, M.x86.R_CX, 0); dev = dev_find_device(M.x86.R_DX, M.x86.R_CX, 0);
if (dev != 0) { if (dev != 0) {
DEBUG_PRINTF_INTR DEBUG_PRINTF_INTR
@ -384,7 +384,7 @@ handleInt1a(void)
offs = M.x86.R_DI; offs = M.x86.R_DI;
DEBUG_PRINTF_INTR("%s(): function: %x: PCI Config Read from device: bus: %02x, devfn: %02x, offset: %02x\n", DEBUG_PRINTF_INTR("%s(): function: %x: PCI Config Read from device: bus: %02x, devfn: %02x, offset: %02x\n",
__func__, M.x86.R_AX, bus, devfn, offs); __func__, M.x86.R_AX, bus, devfn, offs);
#if defined(CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES) && CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES==1 #if CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES
dev = dev_find_slot(bus, devfn); dev = dev_find_slot(bus, devfn);
DEBUG_PRINTF_INTR("%s(): function: %x: dev_find_slot() returned: %s\n", DEBUG_PRINTF_INTR("%s(): function: %x: dev_find_slot() returned: %s\n",
__func__, M.x86.R_AX, dev_path(dev)); __func__, M.x86.R_AX, dev_path(dev));
@ -408,7 +408,7 @@ handleInt1a(void)
switch (M.x86.R_AX) { switch (M.x86.R_AX) {
case 0xb108: case 0xb108:
M.x86.R_CL = M.x86.R_CL =
#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL #if CONFIG_PCI_OPTION_ROM_RUN_YABEL
pci_read_config8(dev, offs); pci_read_config8(dev, offs);
#else #else
(u8) rtas_pci_config_read(bios_device. (u8) rtas_pci_config_read(bios_device.
@ -423,7 +423,7 @@ handleInt1a(void)
break; break;
case 0xb109: case 0xb109:
M.x86.R_CX = M.x86.R_CX =
#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL #if CONFIG_PCI_OPTION_ROM_RUN_YABEL
pci_read_config16(dev, offs); pci_read_config16(dev, offs);
#else #else
(u16) rtas_pci_config_read(bios_device. (u16) rtas_pci_config_read(bios_device.
@ -438,7 +438,7 @@ handleInt1a(void)
break; break;
case 0xb10a: case 0xb10a:
M.x86.R_ECX = M.x86.R_ECX =
#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL #if CONFIG_PCI_OPTION_ROM_RUN_YABEL
pci_read_config32(dev, offs); pci_read_config32(dev, offs);
#else #else
(u32) rtas_pci_config_read(bios_device. (u32) rtas_pci_config_read(bios_device.
@ -476,7 +476,7 @@ handleInt1a(void)
} else { } else {
switch (M.x86.R_AX) { switch (M.x86.R_AX) {
case 0xb10b: case 0xb10b:
#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL #if CONFIG_PCI_OPTION_ROM_RUN_YABEL
pci_write_config8(bios_device.dev, offs, M.x86.R_CL); pci_write_config8(bios_device.dev, offs, M.x86.R_CL);
#else #else
rtas_pci_config_write(bios_device.puid, 1, bus, rtas_pci_config_write(bios_device.puid, 1, bus,
@ -488,7 +488,7 @@ handleInt1a(void)
M.x86.R_CL); M.x86.R_CL);
break; break;
case 0xb10c: case 0xb10c:
#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL #if CONFIG_PCI_OPTION_ROM_RUN_YABEL
pci_write_config16(bios_device.dev, offs, M.x86.R_CX); pci_write_config16(bios_device.dev, offs, M.x86.R_CX);
#else #else
rtas_pci_config_write(bios_device.puid, 2, bus, rtas_pci_config_write(bios_device.puid, 2, bus,
@ -500,7 +500,7 @@ handleInt1a(void)
M.x86.R_CX); M.x86.R_CX);
break; break;
case 0xb10d: case 0xb10d:
#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL #if CONFIG_PCI_OPTION_ROM_RUN_YABEL
pci_write_config32(bios_device.dev, offs, M.x86.R_ECX); pci_write_config32(bios_device.dev, offs, M.x86.R_ECX);
#else #else
rtas_pci_config_write(bios_device.puid, 4, bus, rtas_pci_config_write(bios_device.puid, 4, bus,
@ -576,8 +576,9 @@ handleInterrupt(int intNum)
int_handled = 1; int_handled = 1;
break; break;
case PMM_INT_NUM: case PMM_INT_NUM:
/* the selfdefined PMM INT number, this is called by the code in PMM struct, it /* The self-defined PMM INT number, this is called by
* is handled by pmm_handleInt() * the code in PMM struct, and it is handled by
* pmm_handleInt()
*/ */
pmm_handleInt(); pmm_handleInt();
int_handled = 1; int_handled = 1;

12
src/devices/oprom/yabel/io.c
View File

@ -19,13 +19,13 @@
#include <x86emu/x86emu.h> #include <x86emu/x86emu.h>
#include "io.h" #include "io.h"
#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL #if CONFIG_PCI_OPTION_ROM_RUN_YABEL
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/resource.h> #include <device/resource.h>
#endif #endif
#ifdef CONFIG_ARCH_X86 #if CONFIG_ARCH_X86
#include <arch/io.h> #include <arch/io.h>
#else #else
// these are not used, only needed for linking, must be overridden using X86emu_setupPioFuncs // these are not used, only needed for linking, must be overridden using X86emu_setupPioFuncs
@ -76,7 +76,7 @@ inl(u16 port)
} }
#endif #endif
#if defined(CONFIG_YABEL_DIRECTHW) && (CONFIG_YABEL_DIRECTHW == 1) #if CONFIG_YABEL_DIRECTHW
u8 my_inb(X86EMU_pioAddr addr) u8 my_inb(X86EMU_pioAddr addr)
{ {
u8 val; u8 val;
@ -455,7 +455,7 @@ pci_cfg_read(X86EMU_pioAddr addr, u8 size)
offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly
DEBUG_PRINTF_INTR("%s(): PCI Config Read from device: bus: %02x, devfn: %02x, offset: %02x\n", DEBUG_PRINTF_INTR("%s(): PCI Config Read from device: bus: %02x, devfn: %02x, offset: %02x\n",
__func__, bus, devfn, offs); __func__, bus, devfn, offs);
#if defined(CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES) && CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES==1 #if CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES
dev = dev_find_slot(bus, devfn); dev = dev_find_slot(bus, devfn);
DEBUG_PRINTF_INTR("%s(): dev_find_slot() returned: %s\n", DEBUG_PRINTF_INTR("%s(): dev_find_slot() returned: %s\n",
__func__, dev_path(dev)); __func__, dev_path(dev));
@ -475,7 +475,7 @@ pci_cfg_read(X86EMU_pioAddr addr, u8 size)
HALT_SYS(); HALT_SYS();
return 0; return 0;
} else { } else {
#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL #if CONFIG_PCI_OPTION_ROM_RUN_YABEL
switch (size) { switch (size) {
case 1: case 1:
rval = pci_read_config8(dev, offs); rval = pci_read_config8(dev, offs);
@ -526,7 +526,7 @@ pci_cfg_write(X86EMU_pioAddr addr, u32 val, u8 size)
bus, devfn >> 3, devfn & 7, offs); bus, devfn >> 3, devfn & 7, offs);
HALT_SYS(); HALT_SYS();
} else { } else {
#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL #if CONFIG_PCI_OPTION_ROM_RUN_YABEL
switch (size) { switch (size) {
case 1: case 1:
pci_write_config8(bios_device.dev, offs, val); pci_write_config8(bios_device.dev, offs, val);

4
src/devices/oprom/yabel/mem.c
View File

@ -19,9 +19,9 @@
#include "mem.h" #include "mem.h"
#include "compat/time.h" #include "compat/time.h"
#if !defined(CONFIG_YABEL_DIRECTHW) || (!CONFIG_YABEL_DIRECTHW) #if !CONFIG_YABEL_DIRECTHW || !CONFIG_YABEL_DIRECTHW
#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL #if CONFIG_PCI_OPTION_ROM_RUN_YABEL
#include <device/resource.h> #include <device/resource.h>
#endif #endif

2
src/devices/pci_rom.c
View File

@ -46,7 +46,7 @@ struct rom_header *pci_rom_probe(struct device *dev)
rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS); rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS);
if (rom_address == 0x00000000 || rom_address == 0xffffffff) { if (rom_address == 0x00000000 || rom_address == 0xffffffff) {
#if defined(CONFIG_BOARD_EMULATION_QEMU_X86) && CONFIG_BOARD_EMULATION_QEMU_X86 #if CONFIG_BOARD_EMULATION_QEMU_X86
if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
rom_address = 0xc0000; rom_address = 0xc0000;
else else

4
src/devices/pciexp_device.c
View File

@ -27,7 +27,7 @@
static void pciexp_tune_dev(device_t dev) static void pciexp_tune_dev(device_t dev)
{ {
unsigned int cap; unsigned int cap;
#ifdef CONFIG_PCIE_TUNING #if CONFIG_PCIE_TUNING
u32 reg32; u32 reg32;
#endif #endif
@ -35,7 +35,7 @@ static void pciexp_tune_dev(device_t dev)
if (!cap) if (!cap)
return; return;
#ifdef CONFIG_PCIE_TUNING #if CONFIG_PCIE_TUNING
printk(BIOS_DEBUG, "PCIe: tuning %s\n", dev_path(dev)); printk(BIOS_DEBUG, "PCIe: tuning %s\n", dev_path(dev));
// TODO make this depending on ASPM. // TODO make this depending on ASPM.

4
src/include/cpu/x86/mtrr.h
View File

@ -1,7 +1,6 @@
#ifndef CPU_X86_MTRR_H #ifndef CPU_X86_MTRR_H
#define CPU_X86_MTRR_H #define CPU_X86_MTRR_H
/* These are the region types */ /* These are the region types */
#define MTRR_TYPE_UNCACHEABLE 0 #define MTRR_TYPE_UNCACHEABLE 0
#define MTRR_TYPE_WRCOMB 1 #define MTRR_TYPE_WRCOMB 1
@ -64,11 +63,10 @@ void x86_setup_fixed_mtrrs(void);
# error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE" # error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE"
#endif #endif
#if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0 #if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0
# error "CONFIG_RAMTOP must be a power of 2" # error "CONFIG_RAMTOP must be a power of 2"
#endif #endif
#if !defined (__ASSEMBLER__) #if !defined (__ASSEMBLER__)
#if defined(CONFIG_XIP_ROM_SIZE) #if defined(CONFIG_XIP_ROM_SIZE)
# if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK # if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK

6
src/mainboard/kontron/986lcd-m/mainboard.c
View File

@ -20,14 +20,14 @@
#include <types.h> #include <types.h>
#include <device/device.h> #include <device/device.h>
#include <console/console.h> #include <console/console.h>
#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL #if CONFIG_PCI_OPTION_ROM_RUN_YABEL
#include <x86emu/x86emu.h> #include <x86emu/x86emu.h>
#endif #endif
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include <arch/io.h> #include <arch/io.h>
#include "chip.h" #include "chip.h"
#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL #if CONFIG_PCI_OPTION_ROM_RUN_YABEL
static int int15_handler(void) static int int15_handler(void)
{ {
#define BOOT_DISPLAY_DEFAULT 0 #define BOOT_DISPLAY_DEFAULT 0
@ -221,7 +221,7 @@ static void verb_setup(void)
static void mainboard_enable(device_t dev) static void mainboard_enable(device_t dev)
{ {
#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL #if CONFIG_PCI_OPTION_ROM_RUN_YABEL
/* Install custom int15 handler for VGA OPROM */ /* Install custom int15 handler for VGA OPROM */
int15_install(); int15_install();
#endif #endif

2
src/northbridge/intel/i82830/smihandler.c
View File

@ -37,7 +37,7 @@ extern u32 mbi_len;
/* If YABEL is enabled and it's not running at 0x00000000, we have to add some /* If YABEL is enabled and it's not running at 0x00000000, we have to add some
* offset to all our mbi object memory accesses * offset to all our mbi object memory accesses
*/ */
#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL && !CONFIG_YABEL_DIRECTHW #if CONFIG_PCI_OPTION_ROM_RUN_YABEL && !CONFIG_YABEL_DIRECTHW
#define OBJ_OFFSET CONFIG_YABEL_VIRTMEM_LOCATION #define OBJ_OFFSET CONFIG_YABEL_VIRTMEM_LOCATION
#else #else
#define OBJ_OFFSET 0x00000 #define OBJ_OFFSET 0x00000

4
src/northbridge/intel/i82830/vga.c
View File

@ -25,7 +25,7 @@
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <cbfs.h> #include <cbfs.h>
#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL #if CONFIG_PCI_OPTION_ROM_RUN_YABEL
#include <x86emu/x86emu.h> #include <x86emu/x86emu.h>
#endif #endif
@ -62,7 +62,7 @@ static void vga_init(device_t dev)
printk(BIOS_INFO, "Graphics Initialization Complete\n"); printk(BIOS_INFO, "Graphics Initialization Complete\n");
/* Enable TV-Out */ /* Enable TV-Out */
#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL #if CONFIG_PCI_OPTION_ROM_RUN_YABEL
#define PIPE_A_CRT (1 << 0) #define PIPE_A_CRT (1 << 0)
#define PIPE_A_LFP (1 << 1) #define PIPE_A_LFP (1 << 1)
#define PIPE_A_TV (1 << 3) #define PIPE_A_TV (1 << 3)

18
src/northbridge/intel/i945/raminit.c
View File

@ -113,7 +113,7 @@ void sdram_dump_mchbar_registers(void)
static int memclk(void) static int memclk(void)
{ {
int offset = 0; int offset = 0;
#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) #if CONFIG_NORTHBRIDGE_INTEL_I945GM
offset++; offset++;
#endif #endif
switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) { switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) {
@ -125,7 +125,7 @@ static int memclk(void)
return -1; return -1;
} }
#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) #if CONFIG_NORTHBRIDGE_INTEL_I945GM
static u16 fsbclk(void) static u16 fsbclk(void)
{ {
switch (MCHBAR32(CLKCFG) & 7) { switch (MCHBAR32(CLKCFG) & 7) {
@ -136,7 +136,7 @@ static u16 fsbclk(void)
} }
return 0xffff; return 0xffff;
} }
#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC) #elif CONFIG_NORTHBRIDGE_INTEL_I945GC
static u16 fsbclk(void) static u16 fsbclk(void)
{ {
switch (MCHBAR32(CLKCFG) & 7) { switch (MCHBAR32(CLKCFG) & 7) {
@ -1075,7 +1075,7 @@ static const u32 *slew_group_lookup(int dual_channel, int index)
return nc; return nc;
} }
#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) #if CONFIG_NORTHBRIDGE_INTEL_I945GM
/* Strength multiplier tables */ /* Strength multiplier tables */
static const u8 dual_channel_strength_multiplier[] = { static const u8 dual_channel_strength_multiplier[] = {
0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
@ -1130,7 +1130,7 @@ static const u8 single_channel_strength_multiplier[] = {
0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11 0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11
}; };
#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC) #elif CONFIG_NORTHBRIDGE_INTEL_I945GC
static const u8 dual_channel_strength_multiplier[] = { static const u8 dual_channel_strength_multiplier[] = {
0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
@ -2186,7 +2186,7 @@ static void sdram_program_clock_crossing(void)
/** /**
* We add the indices according to our clocks from CLKCFG. * We add the indices according to our clocks from CLKCFG.
*/ */
#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) #if CONFIG_NORTHBRIDGE_INTEL_I945GM
static const u32 data_clock_crossing[] = { static const u32 data_clock_crossing[] = {
0x00100401, 0x00000000, /* DDR400 FSB400 */ 0x00100401, 0x00000000, /* DDR400 FSB400 */
0xffffffff, 0xffffffff, /* nonexistant */ 0xffffffff, 0xffffffff, /* nonexistant */
@ -2231,7 +2231,7 @@ static void sdram_program_clock_crossing(void)
0xffffffff, 0xffffffff, /* nonexistant */ 0xffffffff, 0xffffffff, /* nonexistant */
}; };
#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC) #elif CONFIG_NORTHBRIDGE_INTEL_I945GC
/* i945 G/P */ /* i945 G/P */
static const u32 data_clock_crossing[] = { static const u32 data_clock_crossing[] = {
0xffffffff, 0xffffffff, /* nonexistant */ 0xffffffff, 0xffffffff, /* nonexistant */
@ -2822,9 +2822,9 @@ static void sdram_enable_memory_clocks(struct sys_info *sysinfo)
{ {
u8 clocks[2] = { 0, 0 }; u8 clocks[2] = { 0, 0 };
#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) #if CONFIG_NORTHBRIDGE_INTEL_I945GM
#define CLOCKS_WIDTH 2 #define CLOCKS_WIDTH 2
#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC) #elif CONFIG_NORTHBRIDGE_INTEL_I945GC
#define CLOCKS_WIDTH 3 #define CLOCKS_WIDTH 3
#endif #endif
if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED)

10
src/southbridge/via/k8t890/early_car.c
View File

@ -69,15 +69,15 @@ u8 k8t890_early_setup_ht(void)
ldtnr = 2; ldtnr = 2;
} }
#if defined(CONFIG_SOUTHBRIDGE_VIA_K8M800) #if CONFIG_SOUTHBRIDGE_VIA_K8M800
print_debug("K8M800 found at LDT "); print_debug("K8M800 found at LDT ");
#elif defined(CONFIG_SOUTHBRIDGE_VIA_K8T800) #elif CONFIG_SOUTHBRIDGE_VIA_K8T800
print_debug("K8T800 found at LDT "); print_debug("K8T800 found at LDT ");
#elif defined(CONFIG_SOUTHBRIDGE_VIA_K8T800PRO) #elif CONFIG_SOUTHBRIDGE_VIA_K8T800PRO
print_debug("K8T800 Pro found at LDT "); print_debug("K8T800 Pro found at LDT ");
#elif defined(CONFIG_SOUTHBRIDGE_VIA_K8M890) #elif CONFIG_SOUTHBRIDGE_VIA_K8M890
print_debug("K8M890 found at LDT "); print_debug("K8M890 found at LDT ");
#elif defined(CONFIG_SOUTHBRIDGE_VIA_K8T890) #elif CONFIG_SOUTHBRIDGE_VIA_K8T890
print_debug("K8T890 found at LDT "); print_debug("K8T890 found at LDT ");
#endif #endif
print_debug_hex8(ldtnr); print_debug_hex8(ldtnr);

2
src/southbridge/via/vt8237r/lpc.c
View File

@ -300,7 +300,7 @@ static void vt8237r_init(struct device *dev)
pci_write_config8(dev, 0x48, 0x0c); pci_write_config8(dev, 0x48, 0x0c);
#else #else
#if defined(CONFIG_SOUTHBRIDGE_VIA_K8T800) #if CONFIG_SOUTHBRIDGE_VIA_K8T800
/* It seems that when we pair with the K8T800, we need to disable /* It seems that when we pair with the K8T800, we need to disable
* the A2 mask * the A2 mask
*/ */

2
src/superio/ite/it8716f/it8716f.h
View File

@ -36,7 +36,7 @@
#define IT8716F_GAME 0x09 /* GAME port */ #define IT8716F_GAME 0x09 /* GAME port */
#define IT8716F_IR 0x0a /* Consumer IR */ #define IT8716F_IR 0x0a /* Consumer IR */
#if defined(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) && CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL #if CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
/* Provided by mainboard, called by IT8716F superio.c. */ /* Provided by mainboard, called by IT8716F superio.c. */
void init_ec(u16 base); void init_ec(u16 base);
#endif #endif

2
src/superio/ite/it8716f/superio.c
View File

@ -46,7 +46,7 @@ static void pnp_exit_ext_func_mode(device_t dev)
pnp_write_config(dev, 0x02, 0x02); pnp_write_config(dev, 0x02, 0x02);
} }
#if !defined(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) || !CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL #if !CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
static void pnp_write_index(u16 port_base, u8 reg, u8 value) static void pnp_write_index(u16 port_base, u8 reg, u8 value)
{ {
outb(reg, port_base); outb(reg, port_base);