Intel 82801dx: compile early_smbus as separate object

Add early_smbus.c for romstage-y list and remove respective
include on mainboard romstage.c files.

Tested on AOpen board.

Change-Id: I1c7e6cb32e3a9d7cc9b6037dc27e59149d492001
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/909
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/mainboard/aopen/dxplplusu/romstage.c

@@ -27,8 +27,6 @@
 #include <cpu/x86/bist.h>
 
 #include "southbridge/intel/i82801dx/i82801dx.h"
-#include "southbridge/intel/i82801dx/early_smbus.c"
-#include "southbridge/intel/i82801dx/reset.c"
 #include "northbridge/intel/e7505/raminit.h"
 
 #include <device/pnp_def.h>

src/mainboard/digitallogic/adl855pc/romstage.c

@@ -10,7 +10,6 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include "southbridge/intel/i82801dx/i82801dx.h"
-#include "southbridge/intel/i82801dx/early_smbus.c"
 #include "northbridge/intel/i855/raminit.h"
 #include "northbridge/intel/i855/debug.c"
 #include "superio/winbond/w83627hf/early_serial.c"

src/mainboard/lanner/em8510/romstage.c

@@ -33,7 +33,6 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include "southbridge/intel/i82801dx/i82801dx.h"
-#include "southbridge/intel/i82801dx/early_smbus.c"
 #include "northbridge/intel/i855/raminit.h"
 #include "northbridge/intel/i855/debug.c"
 #include "superio/winbond/w83627thg/early_serial.c"

src/mainboard/rca/rm4100/romstage.c

@@ -36,7 +36,6 @@
 #include "cpu/x86/bist.h"
 #include "spd_table.h"
 #include "gpio.c"
-#include "southbridge/intel/i82801dx/early_smbus.c"
 #include "southbridge/intel/i82801dx/tco_timer.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)

src/mainboard/thomson/ip1000/romstage.c

@@ -37,7 +37,6 @@
 #include "cpu/x86/bist.h"
 #include "spd_table.h"
 #include "gpio.c"
-#include "southbridge/intel/i82801dx/early_smbus.c"
 #include "southbridge/intel/i82801dx/tco_timer.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)

src/southbridge/intel/i82801dx/Makefile.inc

@@ -31,3 +31,5 @@ ramstage-y += reset.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
+romstage-y += early_smbus.c

src/southbridge/intel/i82801dx/early_smbus.c

@@ -18,26 +18,14 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <console/console.h>
+
 #include "i82801dx.h"
 
-#define SMBHSTSTAT 0x0
+void enable_smbus(void)
-#define SMBHSTCTL  0x2
-#define SMBHSTCMD  0x3
-#define SMBXMITADD 0x4
-#define SMBHSTDAT0 0x5
-#define SMBHSTDAT1 0x6
-#define SMBBLKDAT  0x7
-#define SMBTRNSADD 0x9
-#define SMBSLVDATA 0xa
-#define SMLINK_PIN_CTL 0xe
-#define SMBUS_PIN_CTL  0xf
-
-/* Between 1-10 seconds, We should never timeout normally
- * Longer than this is just painful when a timeout condition occurs.
- */
-//#define SMBUS_TIMEOUT (100*1000*10)
-
-static void enable_smbus(void)
 {
 	device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
 
@@ -112,7 +100,7 @@ static int smbus_wait_until_done(void)
 	return loops ? 0 : -3;
 }
 
-static int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned device, unsigned address)
 {
 	unsigned char global_status_register;
 	unsigned char byte;

src/southbridge/intel/i82801dx/i82801dx.h

@@ -31,9 +31,14 @@
 #ifndef I82801DX_H
 #define I82801DX_H
 
+#if !defined(__ASSEMBLER__) && !defined(__ROMCC__)
 #if !defined(__PRE_RAM__)
 #include "chip.h"
 extern void i82801dx_enable(device_t dev);
+#else
+void enable_smbus(void);
+int smbus_read_byte(unsigned device, unsigned address);
+#endif
 #endif
 
 /*