soc/ti/am335x: Add SDRAM initialization driver
Adds code taken and (barely) adapted from U-Boot (release 2020.04, commit 36fec02b1f90b92cf51ec531564f9284eae27ab4) for SDRAM initialization. This should in theory work for other configurations than the Beaglebone Black's DRAM configuration, but hasn't been tested. Change-Id: Ib1bc2fa606f7010c8c789aa7a5c37cd41bc484b9 Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44386 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sam Lewis
Arthur Heymans
parent
c25d54b97e
commit
1d8d99bfd9
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@ -8,6 +8,7 @@ bootblock-y += mmc.c
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romstage-y += cbmem.c
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romstage-y += timer.c
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romstage-y += mmc.c
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romstage-y += sdram.c
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ramstage-y += timer.c
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ramstage-y += soc.c
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@ -0,0 +1,329 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Taken and adapted from U-Boot.
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*/
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#include "sdram.h"
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#include <types.h>
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#include <device/mmio.h>
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#include <delay.h>
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#include "clock.h"
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static struct vtp_reg *vtpreg[2] = {(struct vtp_reg *)VTP0_CTRL_ADDR,
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(struct vtp_reg *)VTP1_CTRL_ADDR};
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/**
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* Base address for EMIF instances
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*/
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static struct emif_reg_struct *emif_reg[2] = {(struct emif_reg_struct *)EMIF4_0_CFG_BASE,
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(struct emif_reg_struct *)EMIF4_1_CFG_BASE};
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/**
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* Base addresses for DDR PHY cmd/data regs
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*/
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static struct ddr_cmd_regs *ddr_cmd_reg[2] = {(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
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(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};
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static struct ddr_data_regs *ddr_data_reg[2] = {(struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
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(struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};
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/**
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* Base address for ddr io control instances
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*/
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static struct ddr_cmdtctrl *ioctrl_reg = {(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
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struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
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static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
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static void config_vtp(int nr)
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{
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write32(&vtpreg[nr]->vtp0ctrlreg, read32(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE);
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write32(&vtpreg[nr]->vtp0ctrlreg,
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read32(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN));
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write32(&vtpreg[nr]->vtp0ctrlreg, read32(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN);
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/* Poll for READY */
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while ((read32(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) != VTP_CTRL_READY)
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;
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}
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/**
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* Configure SDRAM
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*/
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static void config_sdram(const struct emif_regs *regs, int nr)
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{
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if (regs->zq_config) {
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write32(&emif_reg[nr]->emif_zq_config, regs->zq_config);
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write32(&cstat->secure_emif_sdram_config, regs->sdram_config);
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write32(&emif_reg[nr]->emif_sdram_config, regs->sdram_config);
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/* Trigger initialization */
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write32(&emif_reg[nr]->emif_sdram_ref_ctrl, 0x00003100);
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/* Wait 1ms because of L3 timeout error */
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udelay(1000);
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/* Write proper sdram_ref_cref_ctrl value */
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write32(&emif_reg[nr]->emif_sdram_ref_ctrl, regs->ref_ctrl);
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write32(&emif_reg[nr]->emif_sdram_ref_ctrl_shdw, regs->ref_ctrl);
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}
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write32(&emif_reg[nr]->emif_sdram_ref_ctrl, regs->ref_ctrl);
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write32(&emif_reg[nr]->emif_sdram_ref_ctrl_shdw, regs->ref_ctrl);
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write32(&emif_reg[nr]->emif_sdram_config, regs->sdram_config);
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/* Write REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT. */
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if (regs->ocp_config)
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write32(&emif_reg[nr]->emif_l3_config, regs->ocp_config);
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}
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/**
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* Configure DDR DATA registers
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*/
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static void config_ddr_data(const struct ddr_data *data, int nr)
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{
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int i;
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if (!data)
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return;
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for (i = 0; i < DDR_DATA_REGS_NR; i++) {
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write32(&(ddr_data_reg[nr] + i)->dt0rdsratio0, data->datardsratio0);
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write32(&(ddr_data_reg[nr] + i)->dt0wdsratio0, data->datawdsratio0);
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write32(&(ddr_data_reg[nr] + i)->dt0wiratio0, data->datawiratio0);
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write32(&(ddr_data_reg[nr] + i)->dt0giratio0, data->datagiratio0);
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write32(&(ddr_data_reg[nr] + i)->dt0fwsratio0, data->datafwsratio0);
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write32(&(ddr_data_reg[nr] + i)->dt0wrsratio0, data->datawrsratio0);
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}
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}
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static void config_io_ctrl(const struct ctrl_ioregs *ioregs)
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{
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if (!ioregs)
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return;
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write32(&ioctrl_reg->cm0ioctl, ioregs->cm0ioctl);
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write32(&ioctrl_reg->cm1ioctl, ioregs->cm1ioctl);
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write32(&ioctrl_reg->cm2ioctl, ioregs->cm2ioctl);
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write32(&ioctrl_reg->dt0ioctl, ioregs->dt0ioctl);
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write32(&ioctrl_reg->dt1ioctl, ioregs->dt1ioctl);
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}
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/**
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* Configure DDR CMD control registers
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*/
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static void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
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{
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if (!cmd)
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return;
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write32(&ddr_cmd_reg[nr]->cm0csratio, cmd->cmd0csratio);
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write32(&ddr_cmd_reg[nr]->cm0iclkout, cmd->cmd0iclkout);
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write32(&ddr_cmd_reg[nr]->cm1csratio, cmd->cmd1csratio);
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write32(&ddr_cmd_reg[nr]->cm1iclkout, cmd->cmd1iclkout);
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write32(&ddr_cmd_reg[nr]->cm2csratio, cmd->cmd2csratio);
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write32(&ddr_cmd_reg[nr]->cm2iclkout, cmd->cmd2iclkout);
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}
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static inline uint32_t get_emif_rev(uint32_t base)
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{
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struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
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return (read32(&emif->emif_mod_id_rev) & EMIF_REG_MAJOR_REVISION_MASK)
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>> EMIF_REG_MAJOR_REVISION_SHIFT;
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}
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/*
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* Get SDRAM type connected to EMIF.
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* Assuming similar SDRAM parts are connected to both EMIF's
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* which is typically the case. So it is sufficient to get
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* SDRAM type from EMIF1.
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*/
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static inline uint32_t emif_sdram_type(uint32_t sdram_config)
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{
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return (sdram_config & EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
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}
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/*
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* Configure EXT PHY registers for software leveling
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*/
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static void ext_phy_settings_swlvl(const struct emif_regs *regs, int nr)
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{
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uint32_t *ext_phy_ctrl_base = 0;
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uint32_t *emif_ext_phy_ctrl_base = 0;
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uint32_t i = 0;
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ext_phy_ctrl_base = (uint32_t *)&(regs->emif_ddr_ext_phy_ctrl_1);
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emif_ext_phy_ctrl_base = (uint32_t *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
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/* Configure external phy control timing registers */
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for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
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write32(emif_ext_phy_ctrl_base++, *ext_phy_ctrl_base);
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/* Update shadow registers */
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write32(emif_ext_phy_ctrl_base++, *ext_phy_ctrl_base++);
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}
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}
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/*
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* Configure EXT PHY registers for hardware leveling
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*/
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static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr)
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{
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/*
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* Enable hardware leveling on the EMIF. For details about these
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* magic values please see the EMIF registers section of the TRM.
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*/
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if (regs->emif_ddr_phy_ctlr_1 & 0x00040000) {
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/* PHY_INVERT_CLKOUT = 1 */
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_1, 0x00040100);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw, 0x00040100);
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} else {
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/* PHY_INVERT_CLKOUT = 0 */
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_1, 0x08020080);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw, 0x08020080);
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}
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_22, 0x00000000);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw, 0x00000000);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_23, 0x00600020);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw, 0x00600020);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_24, 0x40010080);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw, 0x40010080);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_25, 0x08102040);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw, 0x08102040);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_26, 0x00200020);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw, 0x00200020);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_27, 0x00200020);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw, 0x00200020);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_28, 0x00200020);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw, 0x00200020);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_29, 0x00200020);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw, 0x00200020);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_30, 0x00200020);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw, 0x00200020);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_31, 0x00000000);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw, 0x00000000);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_32, 0x00000000);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw, 0x00000000);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_33, 0x00000000);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw, 0x00000000);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_34, 0x00000000);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw, 0x00000000);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_35, 0x00000000);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw, 0x00000000);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36, 0x00000077);
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write32(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw, 0x00000077);
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/*
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* Sequence to ensure that the PHY is again in a known state after
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* hardware leveling.
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*/
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write32(&emif_reg[nr]->emif_iodft_tlgc, 0x2011);
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write32(&emif_reg[nr]->emif_iodft_tlgc, 0x2411);
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write32(&emif_reg[nr]->emif_iodft_tlgc, 0x2011);
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}
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/**
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* Configure DDR PHY
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*/
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static void config_ddr_phy(const struct emif_regs *regs, int nr)
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{
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/*
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* Disable initialization and refreshes for now until we finish
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* programming EMIF regs and set time between rising edge of
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* DDR_RESET to rising edge of DDR_CKE to > 500us per memory spec.
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* We currently hardcode a value based on a max expected frequency
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* of 400MHz.
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*/
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write32(&emif_reg[nr]->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK | 0x3100);
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write32(&emif_reg[nr]->emif_ddr_phy_ctrl_1, regs->emif_ddr_phy_ctlr_1);
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write32(&emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw, regs->emif_ddr_phy_ctlr_1);
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if (get_emif_rev((uint32_t)emif_reg[nr]) == EMIF_4D5) {
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if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
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ext_phy_settings_hwlvl(regs, nr);
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else
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ext_phy_settings_swlvl(regs, nr);
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}
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}
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/**
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* Set SDRAM timings
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*/
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static void set_sdram_timings(const struct emif_regs *regs, int nr)
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{
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write32(&emif_reg[nr]->emif_sdram_tim_1, regs->sdram_tim1);
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write32(&emif_reg[nr]->emif_sdram_tim_1_shdw, regs->sdram_tim1);
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write32(&emif_reg[nr]->emif_sdram_tim_2, regs->sdram_tim2);
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write32(&emif_reg[nr]->emif_sdram_tim_2_shdw, regs->sdram_tim2);
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write32(&emif_reg[nr]->emif_sdram_tim_3, regs->sdram_tim3);
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write32(&emif_reg[nr]->emif_sdram_tim_3_shdw, regs->sdram_tim3);
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}
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static void ddr_pll_config(uint32_t ddrpll_m)
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{
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uint32_t clkmode, clksel, div_m2;
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clkmode = read32(&am335x_cm_wkup->clkmode_dpll_ddr);
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clksel = read32(&am335x_cm_wkup->clksel_dpll_ddr);
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div_m2 = read32(&am335x_cm_wkup->div_m2_dpll_ddr);
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/* Set the PLL to bypass Mode */
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clkmode = (clkmode & CLK_MODE_MASK) | PLL_BYPASS_MODE;
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write32(&am335x_cm_wkup->clkmode_dpll_ddr, clkmode);
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/* Wait till bypass mode is enabled */
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while ((read32(&am335x_cm_wkup->idlest_dpll_ddr) & ST_MN_BYPASS) != ST_MN_BYPASS)
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;
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clksel = clksel & (~CLK_SEL_MASK);
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clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N);
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write32(&am335x_cm_wkup->clksel_dpll_ddr, clksel);
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div_m2 = div_m2 & CLK_DIV_SEL;
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div_m2 = div_m2 | DDRPLL_M2;
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write32(&am335x_cm_wkup->div_m2_dpll_ddr, div_m2);
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clkmode = (clkmode & CLK_MODE_MASK) | CLK_MODE_SEL;
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write32(&am335x_cm_wkup->clkmode_dpll_ddr, clkmode);
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/* Wait till dpll is locked */
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while ((read32(&am335x_cm_wkup->idlest_dpll_ddr) & ST_DPLL_CLK) != ST_DPLL_CLK)
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;
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}
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static void enable_emif_clocks(void)
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{
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/* Enable EMIF0 Clock */
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write32(&am335x_cm_per->emif, CM_MODULEMODE_ENABLED);
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/* Poll if module is functional */
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while ((read32(&am335x_cm_per->emif)) != CM_MODULEMODE_ENABLED)
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;
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}
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void config_ddr(uint32_t pll, const struct ctrl_ioregs *ioregs, const struct ddr_data *data,
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const struct cmd_control *ctrl, const struct emif_regs *regs, int nr)
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{
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enable_emif_clocks();
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ddr_pll_config(pll);
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config_vtp(nr);
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config_cmd_ctrl(ctrl, nr);
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config_ddr_data(data, nr);
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config_io_ctrl(ioregs);
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/* Set CKE to be controlled by EMIF/DDR PHY */
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write32(&ddrctrl->ddrckectrl, DDR_CKE_CTRL_NORMAL);
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/* Program EMIF instance */
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config_ddr_phy(regs, nr);
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set_sdram_timings(regs, nr);
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config_sdram(regs, nr);
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}
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@ -0,0 +1,384 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __CPU_TI_AM335X_DDR_INIT_H__
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#define __CPU_TI_AM335X_DDR_INIT_H__
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#include <types.h>
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struct ctrl_ioregs {
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uint32_t cm0ioctl;
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uint32_t cm1ioctl;
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uint32_t cm2ioctl;
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uint32_t dt0ioctl;
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uint32_t dt1ioctl;
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uint32_t dt2ioctrl;
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uint32_t dt3ioctrl;
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uint32_t emif_sdram_config_ext;
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};
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/**
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* Encapsulates DDR DATA registers.
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*/
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struct ddr_data {
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uint32_t datardsratio0;
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uint32_t datawdsratio0;
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uint32_t datawiratio0;
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uint32_t datagiratio0;
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||||
uint32_t datafwsratio0;
|
||||
uint32_t datawrsratio0;
|
||||
};
|
||||
|
||||
/**
|
||||
* Encapsulates DDR CMD control registers.
|
||||
*/
|
||||
struct cmd_control {
|
||||
uint32_t cmd0csratio;
|
||||
uint32_t cmd0csforce;
|
||||
uint32_t cmd0csdelay;
|
||||
uint32_t cmd0iclkout;
|
||||
uint32_t cmd1csratio;
|
||||
uint32_t cmd1csforce;
|
||||
uint32_t cmd1csdelay;
|
||||
uint32_t cmd1iclkout;
|
||||
uint32_t cmd2csratio;
|
||||
uint32_t cmd2csforce;
|
||||
uint32_t cmd2csdelay;
|
||||
uint32_t cmd2iclkout;
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Structure containing shadow of important registers in EMIF
|
||||
* The calculation function fills in this structure to be later used for
|
||||
* initialization and DVFS
|
||||
*/
|
||||
struct emif_regs {
|
||||
uint32_t freq;
|
||||
uint32_t sdram_config_init;
|
||||
uint32_t sdram_config;
|
||||
uint32_t sdram_config2;
|
||||
uint32_t ref_ctrl;
|
||||
uint32_t ref_ctrl_final;
|
||||
uint32_t sdram_tim1;
|
||||
uint32_t sdram_tim2;
|
||||
uint32_t sdram_tim3;
|
||||
uint32_t ocp_config;
|
||||
uint32_t read_idle_ctrl;
|
||||
uint32_t zq_config;
|
||||
uint32_t temp_alert_config;
|
||||
uint32_t emif_ddr_phy_ctlr_1_init;
|
||||
uint32_t emif_ddr_phy_ctlr_1;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_1;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_2;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_3;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_4;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_5;
|
||||
uint32_t emif_rd_wr_lvl_rmp_win;
|
||||
uint32_t emif_rd_wr_lvl_rmp_ctl;
|
||||
uint32_t emif_rd_wr_lvl_ctl;
|
||||
uint32_t emif_rd_wr_exec_thresh;
|
||||
uint32_t emif_prio_class_serv_map;
|
||||
uint32_t emif_connect_id_serv_1_map;
|
||||
uint32_t emif_connect_id_serv_2_map;
|
||||
uint32_t emif_cos_config;
|
||||
uint32_t emif_ecc_ctrl_reg;
|
||||
uint32_t emif_ecc_address_range_1;
|
||||
uint32_t emif_ecc_address_range_2;
|
||||
};
|
||||
|
||||
/* VTP Registers */
|
||||
struct vtp_reg {
|
||||
uint32_t vtp0ctrlreg;
|
||||
};
|
||||
|
||||
|
||||
/* Reg mapping structure */
|
||||
struct emif_reg_struct {
|
||||
uint32_t emif_mod_id_rev;
|
||||
uint32_t emif_status;
|
||||
uint32_t emif_sdram_config;
|
||||
uint32_t emif_lpddr2_nvm_config;
|
||||
uint32_t emif_sdram_ref_ctrl;
|
||||
uint32_t emif_sdram_ref_ctrl_shdw;
|
||||
uint32_t emif_sdram_tim_1;
|
||||
uint32_t emif_sdram_tim_1_shdw;
|
||||
uint32_t emif_sdram_tim_2;
|
||||
uint32_t emif_sdram_tim_2_shdw;
|
||||
uint32_t emif_sdram_tim_3;
|
||||
uint32_t emif_sdram_tim_3_shdw;
|
||||
uint32_t emif_lpddr2_nvm_tim;
|
||||
uint32_t emif_lpddr2_nvm_tim_shdw;
|
||||
uint32_t emif_pwr_mgmt_ctrl;
|
||||
uint32_t emif_pwr_mgmt_ctrl_shdw;
|
||||
uint32_t emif_lpddr2_mode_reg_data;
|
||||
uint32_t padding1[1];
|
||||
uint32_t emif_lpddr2_mode_reg_data_es2;
|
||||
uint32_t padding11[1];
|
||||
uint32_t emif_lpddr2_mode_reg_cfg;
|
||||
uint32_t emif_l3_config;
|
||||
uint32_t emif_l3_cfg_val_1;
|
||||
uint32_t emif_l3_cfg_val_2;
|
||||
uint32_t emif_iodft_tlgc;
|
||||
uint32_t padding2[7];
|
||||
uint32_t emif_perf_cnt_1;
|
||||
uint32_t emif_perf_cnt_2;
|
||||
uint32_t emif_perf_cnt_cfg;
|
||||
uint32_t emif_perf_cnt_sel;
|
||||
uint32_t emif_perf_cnt_tim;
|
||||
uint32_t padding3;
|
||||
uint32_t emif_read_idlectrl;
|
||||
uint32_t emif_read_idlectrl_shdw;
|
||||
uint32_t padding4;
|
||||
uint32_t emif_irqstatus_raw_sys;
|
||||
uint32_t emif_irqstatus_raw_ll;
|
||||
uint32_t emif_irqstatus_sys;
|
||||
uint32_t emif_irqstatus_ll;
|
||||
uint32_t emif_irqenable_set_sys;
|
||||
uint32_t emif_irqenable_set_ll;
|
||||
uint32_t emif_irqenable_clr_sys;
|
||||
uint32_t emif_irqenable_clr_ll;
|
||||
uint32_t padding5;
|
||||
uint32_t emif_zq_config;
|
||||
uint32_t emif_temp_alert_config;
|
||||
uint32_t emif_l3_err_log;
|
||||
uint32_t emif_rd_wr_lvl_rmp_win;
|
||||
uint32_t emif_rd_wr_lvl_rmp_ctl;
|
||||
uint32_t emif_rd_wr_lvl_ctl;
|
||||
uint32_t padding6[1];
|
||||
uint32_t emif_ddr_phy_ctrl_1;
|
||||
uint32_t emif_ddr_phy_ctrl_1_shdw;
|
||||
uint32_t emif_ddr_phy_ctrl_2;
|
||||
uint32_t padding7[4];
|
||||
uint32_t emif_prio_class_serv_map;
|
||||
uint32_t emif_connect_id_serv_1_map;
|
||||
uint32_t emif_connect_id_serv_2_map;
|
||||
uint32_t padding8;
|
||||
uint32_t emif_ecc_ctrl_reg;
|
||||
uint32_t emif_ecc_address_range_1;
|
||||
uint32_t emif_ecc_address_range_2;
|
||||
uint32_t padding8_1;
|
||||
uint32_t emif_rd_wr_exec_thresh;
|
||||
uint32_t emif_cos_config;
|
||||
uint32_t padding9[6];
|
||||
uint32_t emif_ddr_phy_status[28];
|
||||
uint32_t padding10[20];
|
||||
uint32_t emif_ddr_ext_phy_ctrl_1;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_1_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_2;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_2_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_3;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_3_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_4;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_4_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_5;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_5_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_6;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_6_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_7;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_7_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_8;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_8_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_9;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_9_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_10;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_10_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_11;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_11_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_12;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_12_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_13;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_13_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_14;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_14_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_15;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_15_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_16;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_16_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_17;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_17_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_18;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_18_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_19;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_19_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_20;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_20_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_21;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_21_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_22;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_22_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_23;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_23_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_24;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_24_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_25;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_25_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_26;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_26_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_27;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_27_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_28;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_28_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_29;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_29_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_30;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_30_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_31;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_31_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_32;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_32_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_33;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_33_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_34;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_34_shdw;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_35;
|
||||
uint32_t emif_ddr_ext_phy_ctrl_35_shdw;
|
||||
union {
|
||||
uint32_t emif_ddr_ext_phy_ctrl_36;
|
||||
uint32_t emif_ddr_fifo_misaligned_clear_1;
|
||||
};
|
||||
union {
|
||||
uint32_t emif_ddr_ext_phy_ctrl_36_shdw;
|
||||
uint32_t emif_ddr_fifo_misaligned_clear_2;
|
||||
};
|
||||
};
|
||||
|
||||
struct ddr_cmd_regs {
|
||||
uint32_t resv0[7];
|
||||
uint32_t cm0csratio; /* offset 0x01C */
|
||||
uint32_t resv1[3];
|
||||
uint32_t cm0iclkout; /* offset 0x02C */
|
||||
uint32_t resv2[8];
|
||||
uint32_t cm1csratio; /* offset 0x050 */
|
||||
uint32_t resv3[3];
|
||||
uint32_t cm1iclkout; /* offset 0x060 */
|
||||
uint32_t resv4[8];
|
||||
uint32_t cm2csratio; /* offset 0x084 */
|
||||
uint32_t resv5[3];
|
||||
uint32_t cm2iclkout; /* offset 0x094 */
|
||||
uint32_t resv6[3];
|
||||
};
|
||||
|
||||
struct ddr_data_regs {
|
||||
uint32_t dt0rdsratio0; /* offset 0x0C8 */
|
||||
uint32_t resv1[4];
|
||||
uint32_t dt0wdsratio0; /* offset 0x0DC */
|
||||
uint32_t resv2[4];
|
||||
uint32_t dt0wiratio0; /* offset 0x0F0 */
|
||||
uint32_t resv3;
|
||||
uint32_t dt0wimode0; /* offset 0x0F8 */
|
||||
uint32_t dt0giratio0; /* offset 0x0FC */
|
||||
uint32_t resv4;
|
||||
uint32_t dt0gimode0; /* offset 0x104 */
|
||||
uint32_t dt0fwsratio0; /* offset 0x108 */
|
||||
uint32_t resv5[4];
|
||||
uint32_t dt0dqoffset; /* offset 0x11C */
|
||||
uint32_t dt0wrsratio0; /* offset 0x120 */
|
||||
uint32_t resv6[4];
|
||||
uint32_t dt0rdelays0; /* offset 0x134 */
|
||||
uint32_t dt0dldiff0; /* offset 0x138 */
|
||||
uint32_t resv7[12];
|
||||
};
|
||||
|
||||
/* Control Status Register */
|
||||
struct ctrl_stat {
|
||||
uint32_t resv1[16];
|
||||
uint32_t statusreg; /* ofset 0x40 */
|
||||
uint32_t resv2[51];
|
||||
uint32_t secure_emif_sdram_config; /* offset 0x0110 */
|
||||
uint32_t resv3[319];
|
||||
uint32_t dev_attr;
|
||||
};
|
||||
|
||||
/**
|
||||
* This structure represents the DDR io control on AM33XX devices.
|
||||
*/
|
||||
struct ddr_cmdtctrl {
|
||||
uint32_t cm0ioctl;
|
||||
uint32_t cm1ioctl;
|
||||
uint32_t cm2ioctl;
|
||||
uint32_t resv2[12];
|
||||
uint32_t dt0ioctl;
|
||||
uint32_t dt1ioctl;
|
||||
uint32_t dt2ioctrl;
|
||||
uint32_t dt3ioctrl;
|
||||
uint32_t resv3[4];
|
||||
uint32_t emif_sdram_config_ext;
|
||||
};
|
||||
|
||||
struct ddr_ctrl {
|
||||
uint32_t ddrioctrl;
|
||||
uint32_t resv1[325];
|
||||
uint32_t ddrckectrl;
|
||||
};
|
||||
|
||||
/* AM335X EMIF Register values */
|
||||
#define VTP_CTRL_READY (0x1 << 5)
|
||||
#define VTP_CTRL_ENABLE (0x1 << 6)
|
||||
#define VTP_CTRL_START_EN (0x1)
|
||||
|
||||
#define DDR_CKE_CTRL_NORMAL 0x1
|
||||
|
||||
#define PHY_EN_DYN_PWRDN (0x1 << 20)
|
||||
|
||||
/* VTP Base address */
|
||||
#define VTP0_CTRL_ADDR 0x44E10E0C
|
||||
#define VTP1_CTRL_ADDR 0x48140E10
|
||||
|
||||
/* EMIF Base address */
|
||||
#define EMIF4_0_CFG_BASE 0x4C000000
|
||||
#define EMIF4_1_CFG_BASE 0x4D000000
|
||||
|
||||
/* DDR Base address */
|
||||
#define DDR_PHY_CMD_ADDR 0x44E12000
|
||||
#define DDR_PHY_DATA_ADDR 0x44E120C8
|
||||
#define DDR_PHY_CMD_ADDR2 0x47C0C800
|
||||
#define DDR_PHY_DATA_ADDR2 0x47C0C8C8
|
||||
#define DDR_DATA_REGS_NR 2
|
||||
|
||||
/* DDR Base address */
|
||||
#define DDR_CTRL_ADDR 0x44E10E04
|
||||
#define DDR_CONTROL_BASE_ADDR 0x44E11404
|
||||
|
||||
/* Control Module Base Address */
|
||||
#define CTRL_BASE 0x44E10000
|
||||
|
||||
#define EMIF_REG_MAJOR_REVISION_SHIFT 8
|
||||
#define EMIF_REG_MAJOR_REVISION_MASK (0x7 << 8)
|
||||
|
||||
#define EMIF_REG_SDRAM_TYPE_SHIFT 29
|
||||
#define EMIF_REG_SDRAM_TYPE_MASK (0x7 << 29)
|
||||
|
||||
#define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5
|
||||
|
||||
#define EMIF_REG_INITREF_DIS_MASK (1 << 31)
|
||||
#define EMIF_4D5 0x5
|
||||
|
||||
/* SDRAM TYPE */
|
||||
#define EMIF_SDRAM_TYPE_DDR2 0x2
|
||||
#define EMIF_SDRAM_TYPE_DDR3 0x3
|
||||
#define EMIF_SDRAM_TYPE_LPDDR2 0x4
|
||||
|
||||
#define PLL_BYPASS_MODE 0x4
|
||||
#define ST_MN_BYPASS 0x00000100
|
||||
#define ST_DPLL_CLK 0x00000001
|
||||
#define CLK_SEL_MASK 0x7ffff
|
||||
#define CLK_DIV_MASK 0x1f
|
||||
#define CLK_DIV2_MASK 0x7f
|
||||
#define CLK_SEL_SHIFT 0x8
|
||||
#define CLK_MODE_SEL 0x7
|
||||
#define CLK_MODE_MASK 0xfffffff8
|
||||
#define CLK_DIV_SEL 0xFFFFFFE0
|
||||
#define CPGMAC0_IDLE 0x30000
|
||||
#define DPLL_CLKDCOLDO_GATE_CTRL 0x300
|
||||
|
||||
#define V_OSCK 24000000 /* Clock output from T2 */
|
||||
#define OSC (V_OSCK / 1000000)
|
||||
|
||||
#define DDRPLL_M 266
|
||||
#define DDRPLL_N (OSC - 1)
|
||||
#define DDRPLL_M2 1
|
||||
|
||||
void config_ddr(uint32_t pll, const struct ctrl_ioregs *ioregs, const struct ddr_data *data,
|
||||
const struct cmd_control *ctrl, const struct emif_regs *regs, int nr);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue