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Get rid of AUTO_XIP_ROM_BASE 

That value is now generated from a code address and CONFIG_XIP_ROM_SIZE.
This works as MTRRs are fully specified by their size and any address
within the range.

Change-Id: Id35d34eaf3be37f59cd2a968e3327d333ba71a34
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/348
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Patrick Georgi 2011-10-28 20:28:03 +02:00 committed by Stefan Reinauer
parent 0f8590f9ca
commit 1da104647d
9 changed files with 39 additions and 69 deletions
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4
src/arch/x86/Makefile.bootblock.inc
View File

@ -76,13 +76,13 @@ $(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootbl
# Build the romstage # Build the romstage
$(obj)/coreboot.romstage: $(obj)/coreboot.pre1 $$(romstage-objs) $(obj)/romstage/ldscript.ld $(obj)/coreboot.romstage: $(obj)/coreboot.pre1 $$(romstage-objs) $(obj)/romstage/ldscript.ld
@printf " LINK $(subst $(obj)/,,$(@))\n" @printf " LINK $(subst $(obj)/,,$(@))\n"
printf "CONFIG_ROMBASE = 0x0;\nAUTO_XIP_ROM_BASE = 0x0;\n" > $(obj)/location.ld printf "CONFIG_ROMBASE = 0x0;\n" > $(obj)/location.ld
$(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs) $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs)
$(OBJCOPY) -O binary $(obj)/romstage.elf $(obj)/romstage.bin $(OBJCOPY) -O binary $(obj)/romstage.elf $(obj)/romstage.bin
printf "CONFIG_ROMBASE = 0x" > $(obj)/location.ld printf "CONFIG_ROMBASE = 0x" > $(obj)/location.ld
$(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_XIP_ROM_SIZE) > $(obj)/location.txt $(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_XIP_ROM_SIZE) > $(obj)/location.txt
cat $(obj)/location.txt >> $(obj)/location.ld cat $(obj)/location.txt >> $(obj)/location.ld
printf ';\nAUTO_XIP_ROM_BASE = CONFIG_ROMBASE & ~(CONFIG_XIP_ROM_SIZE - 1);\n' >> $(obj)/location.ld printf ';\n' >> $(obj)/location.ld
$(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs) $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs)
$(NM) -n $(obj)/romstage.elf | sort > $(obj)/romstage.map $(NM) -n $(obj)/romstage.elf | sort > $(obj)/romstage.map
$(OBJCOPY) --only-keep-debug $(obj)/romstage.elf $(obj)/romstage.debug $(OBJCOPY) --only-keep-debug $(obj)/romstage.elf $(obj)/romstage.debug

14
src/cpu/amd/car/cache_as_ram.inc
View File

@ -281,24 +281,18 @@ clear_fixed_var_mtrr_out:
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
#if CONFIG_TINY_BOOTBLOCK
#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
#else
#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
#endif
/* Enable write base caching so we can do execute in place (XIP) /* Enable write base caching so we can do execute in place (XIP)
* on the flash ROM. * on the flash ROM.
*/ */
movl $MTRRphysBase_MSR(1), %ecx movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx xorl %edx, %edx
/* /*
* IMPORTANT: The two lines below can _not_ be written like this: * IMPORTANT: The following calculation _must_ be done at runtime. See
* movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRPROT), %eax
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/ */
movl $REAL_XIP_ROM_BASE, %eax movl copy_and_run, %eax
orl $MTRR_TYPE_WRPROT, %eax andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax
wrmsr wrmsr
movl $MTRRphysMask_MSR(1), %ecx movl $MTRRphysMask_MSR(1), %ecx

12
src/cpu/intel/car/cache_as_ram.inc
View File

@ -231,12 +231,6 @@ clear_fixed_var_mtrr_out:
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
#if CONFIG_TINY_BOOTBLOCK
#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
#else
#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
#endif
/* /*
* Enable write base caching so we can do execute in place (XIP) * Enable write base caching so we can do execute in place (XIP)
* on the flash ROM. * on the flash ROM.
@ -244,11 +238,11 @@ clear_fixed_var_mtrr_out:
movl $MTRRphysBase_MSR(1), %ecx movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx xorl %edx, %edx
/* /*
* IMPORTANT: The two lines below can _not_ be written like this: * IMPORTANT: The following calculation _must_ be done at runtime. See
* movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/ */
movl $REAL_XIP_ROM_BASE, %eax movl copy_and_run, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax orl $MTRR_TYPE_WRBACK, %eax
wrmsr wrmsr

11
src/cpu/intel/model_106cx/cache_as_ram.inc
View File

@ -102,17 +102,12 @@ clear_mtrrs:
/* Enable cache for our code in Flash because we do XIP here */ /* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx xorl %edx, %edx
#if CONFIG_TINY_BOOTBLOCK
#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
#else
#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
#endif
/* /*
* IMPORTANT: The two lines below can _not_ be written like this: * IMPORTANT: The following calculation _must_ be done at runtime. See
* movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/ */
movl $REAL_XIP_ROM_BASE, %eax movl copy_and_run, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax orl $MTRR_TYPE_WRBACK, %eax
wrmsr wrmsr

11
src/cpu/intel/model_6ex/cache_as_ram.inc
View File

@ -102,17 +102,12 @@ clear_mtrrs:
/* Enable cache for our code in Flash because we do XIP here */ /* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx xorl %edx, %edx
#if CONFIG_TINY_BOOTBLOCK
#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
#else
#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
#endif
/* /*
* IMPORTANT: The two lines below can _not_ be written like this: * IMPORTANT: The following calculation _must_ be done at runtime. See
* movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/ */
movl $REAL_XIP_ROM_BASE, %eax movl copy_and_run, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax orl $MTRR_TYPE_WRBACK, %eax
wrmsr wrmsr

11
src/cpu/intel/model_6fx/cache_as_ram.inc
View File

@ -109,17 +109,12 @@ clear_mtrrs:
/* Enable cache for our code in Flash because we do XIP here */ /* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx xorl %edx, %edx
#if CONFIG_TINY_BOOTBLOCK
#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
#else
#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
#endif
/* /*
* IMPORTANT: The two lines below can _not_ be written like this: * IMPORTANT: The following calculation _must_ be done at runtime. See
* movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/ */
movl $REAL_XIP_ROM_BASE, %eax movl copy_and_run, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax orl $MTRR_TYPE_WRBACK, %eax
wrmsr wrmsr

26
src/cpu/via/car/cache_as_ram.inc
View File

@ -110,12 +110,6 @@ clear_fixed_var_mtrr_out:
movl $(~(CacheSize - 1) | MTRRphysMaskValid), %eax movl $(~(CacheSize - 1) | MTRRphysMaskValid), %eax
wrmsr wrmsr
#if CONFIG_TINY_BOOTBLOCK
#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
#else
#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
#endif
/* /*
* Enable write base caching so we can do execute in place (XIP) * Enable write base caching so we can do execute in place (XIP)
* on the flash ROM. * on the flash ROM.
@ -123,11 +117,11 @@ clear_fixed_var_mtrr_out:
movl $MTRRphysBase_MSR(1), %ecx movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx xorl %edx, %edx
/* /*
* IMPORTANT: The two lines below can _not_ be written like this: * IMPORTANT: The following calculation _must_ be done at runtime. See
* movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/ */
movl $REAL_XIP_ROM_BASE, %eax movl copy_and_run, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax orl $MTRR_TYPE_WRBACK, %eax
wrmsr wrmsr
@ -168,7 +162,12 @@ clear_fixed_var_mtrr_out:
rep stosl rep stosl
#ifdef CARTEST #ifdef CARTEST
movl REAL_XIP_ROM_BASE, %esi /*
* IMPORTANT: The following calculation _must_ be done at runtime. See
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
movl copy_and_run, %esi
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %ei
movl %esi, %edi movl %esi, %edi
movl $(CONFIG_XIP_ROM_SIZE >> 2), %ecx movl $(CONFIG_XIP_ROM_SIZE >> 2), %ecx
rep lodsl rep lodsl
@ -244,7 +243,12 @@ testok:
/* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */ /* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */
movl $MTRRphysBase_MSR(1), %ecx movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx xorl %edx, %edx
movl $REAL_XIP_ROM_BASE, %eax /*
* IMPORTANT: The following calculation _must_ be done at runtime. See
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
movl copy_and_run, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax orl $MTRR_TYPE_WRBACK, %eax
wrmsr wrmsr

7
src/cpu/x86/mtrr/earlymtrr.c
View File

@ -29,6 +29,8 @@ static void cache_lbmem(int type)
enable_cache(); enable_cache();
} }
const int addr_det = 0;
/* the fixed and variable MTTRs are power-up with random values, /* the fixed and variable MTTRs are power-up with random values,
* clear them to MTRR_TYPE_UNCACHEABLE for safty. * clear them to MTRR_TYPE_UNCACHEABLE for safty.
*/ */
@ -52,8 +54,11 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
#if defined(CONFIG_XIP_ROM_SIZE) #if defined(CONFIG_XIP_ROM_SIZE)
/* enable write through caching so we can do execute in place /* enable write through caching so we can do execute in place
* on the flash rom. * on the flash rom.
* Determine address by calculating the XIP_ROM_SIZE sized area with
* XIP_ROM_SIZE alignment that contains the global variable defined above;
*/ */
set_var_mtrr(1, REAL_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK); unsigned long f = (unsigned long)&addr_det & ~(CONFIG_XIP_ROM_SIZE - 1);
set_var_mtrr(1, f, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
#endif #endif
/* Set the default memory type and enable fixed and variable MTRRs /* Set the default memory type and enable fixed and variable MTRRs

12
src/include/cpu/x86/mtrr.h
View File

@ -67,16 +67,4 @@ void x86_setup_fixed_mtrrs(void);
# error "CONFIG_RAMTOP must be a power of 2" # error "CONFIG_RAMTOP must be a power of 2"
#endif #endif
#if !defined (__ASSEMBLER__)
#if defined(CONFIG_XIP_ROM_SIZE)
# if CONFIG_TINY_BOOTBLOCK
extern unsigned long AUTO_XIP_ROM_BASE;
# define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
# else
# define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
# endif
#endif
#endif
#endif /* CPU_X86_MTRR_H */ #endif /* CPU_X86_MTRR_H */