soc/intel/{cnl, icl}: Update the DCACHE_BSP_STACK_SIZE to 129KiB
The current DCACHE_BSP_STACK_SIZE is set to 128KiB for CML & ICL when FSP uses the same stack provided by coreboot. This patch updates it to 129KiB since the default value of DCACHE_BSP_STACK_SIZE must be the sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB). BUG=b:140268415 TEST=Build and boot CML-Hatch. Change-Id: Icedff8b42e86dc095fb68deb0b8f80b2667cfeda Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36032 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -120,11 +120,12 @@ config DCACHE_RAM_SIZE
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config DCACHE_BSP_STACK_SIZE
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config DCACHE_BSP_STACK_SIZE
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hex
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hex
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default 0x20000 if FSP_USES_CB_STACK
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default 0x20400 if FSP_USES_CB_STACK
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default 0x4000
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default 0x4000
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help
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help
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The amount of anticipated stack usage in CAR by bootblock and
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The amount of anticipated stack usage in CAR by bootblock and
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other stages.
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other stages. In the case of FSP_USES_CB_STACK default value will be
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sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB).
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config FSP_TEMP_RAM_SIZE
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config FSP_TEMP_RAM_SIZE
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hex
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hex
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@ -70,11 +70,12 @@ config DCACHE_RAM_SIZE
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config DCACHE_BSP_STACK_SIZE
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config DCACHE_BSP_STACK_SIZE
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hex
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hex
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default 0x20000 if FSP_USES_CB_STACK
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default 0x20400 if FSP_USES_CB_STACK
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default 0x4000
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default 0x4000
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help
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help
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The amount of anticipated stack usage in CAR by bootblock and
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The amount of anticipated stack usage in CAR by bootblock and
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other stages.
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other stages. In the case of FSP_USES_CB_STACK default value will be
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sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB).
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config FSP_TEMP_RAM_SIZE
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config FSP_TEMP_RAM_SIZE
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hex
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hex
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