src/southbridge: Get rid of device_t
Use of device_t is deprecated. Change-Id: Ib4db9c263ff156966926f9576eed7e3cfb02e78a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Elyes HAOUAS
Patrick Georgi
parent
012ef7735d
commit
1dcd8dbf76
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@ -34,30 +34,54 @@
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#define AB_INDX 0xCD8
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#define AB_DATA (AB_INDX+4)
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static inline u32 nb_read_index(device_t dev, u32 index_reg, u32 index)
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#ifdef __SIMPLE_DEVICE__
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static inline u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index)
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#else
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static inline u32 nb_read_index(struct device *dev, u32 index_reg, u32 index)
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#endif
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{
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pci_write_config32(dev, index_reg, index);
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return pci_read_config32(dev, index_reg + 0x4);
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}
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static inline void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data)
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#ifdef __SIMPLE_DEVICE__
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static inline void nb_write_index(pci_devfn_t dev, u32 index_reg, u32 index,
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u32 data)
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#else
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static inline void nb_write_index(struct device *dev, u32 index_reg, u32 index,
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u32 data)
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#endif
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{
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pci_write_config32(dev, index_reg, index);
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pci_write_config32(dev, index_reg + 0x4, data);
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}
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static inline u32 nbmisc_read_index(device_t nb_dev, u32 index)
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#ifdef __SIMPLE_DEVICE__
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static inline u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index)
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#else
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static inline u32 nbmisc_read_index(struct device *nb_dev, u32 index)
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#endif
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{
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return nb_read_index((nb_dev), NBMISC_INDEX, (index));
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}
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static inline void nbmisc_write_index(device_t nb_dev, u32 index, u32 data)
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#ifdef __SIMPLE_DEVICE__
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static inline void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
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#else
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static inline void nbmisc_write_index(struct device *nb_dev, u32 index,
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u32 data)
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#endif
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{
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nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));
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}
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static inline void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
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u32 val)
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#ifdef __SIMPLE_DEVICE__
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static inline void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,
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u32 mask, u32 val)
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#else
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static inline void set_nbmisc_enable_bits(struct device *nb_dev, u32 reg_pos,
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u32 mask, u32 val)
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#endif
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{
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u32 reg_old, reg;
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reg = reg_old = nbmisc_read_index(nb_dev, reg_pos);
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@ -68,28 +92,49 @@ static inline void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask
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}
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}
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static inline u32 htiu_read_index(device_t nb_dev, u32 index)
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#ifdef __SIMPLE_DEVICE__
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static inline u32 htiu_read_index(pci_devfn_t nb_dev, u32 index)
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#else
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static inline u32 htiu_read_index(struct device *nb_dev, u32 index)
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#endif
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{
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return nb_read_index((nb_dev), NBHTIU_INDEX, (index));
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}
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static inline void htiu_write_index(device_t nb_dev, u32 index, u32 data)
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#ifdef __SIMPLE_DEVICE__
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static inline void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
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#else
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static inline void htiu_write_index(struct device *nb_dev, u32 index, u32 data)
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#endif
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{
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nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));
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}
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static inline u32 nbmc_read_index(device_t nb_dev, u32 index)
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#ifdef __SIMPLE_DEVICE__
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static inline u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index)
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#else
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static inline u32 nbmc_read_index(struct device *nb_dev, u32 index)
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#endif
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{
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return nb_read_index((nb_dev), NBMC_INDEX, (index));
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}
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static inline void nbmc_write_index(device_t nb_dev, u32 index, u32 data)
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#ifdef __SIMPLE_DEVICE__
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static inline void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
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#else
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static inline void nbmc_write_index(struct device *nb_dev, u32 index, u32 data)
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#endif
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{
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nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));
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}
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static inline void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
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u32 val)
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#ifdef __SIMPLE_DEVICE__
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static inline void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,
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u32 mask, u32 val)
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#else
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static inline void set_htiu_enable_bits(struct device *nb_dev, u32 reg_pos,
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u32 mask, u32 val)
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#endif
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{
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u32 reg_old, reg;
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reg = reg_old = htiu_read_index(nb_dev, reg_pos);
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@ -100,8 +145,13 @@ static inline void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
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}
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}
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static inline void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
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u32 val)
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#ifdef __SIMPLE_DEVICE__
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static inline void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,
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u32 mask, u32 val)
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#else
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static inline void set_nbcfg_enable_bits(struct device *nb_dev, u32 reg_pos,
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u32 mask, u32 val)
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#endif
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{
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u32 reg_old, reg;
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reg = reg_old = pci_read_config32(nb_dev, reg_pos);
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@ -112,8 +162,13 @@ static inline void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
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}
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}
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static inline void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask,
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u8 val)
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#ifdef __SIMPLE_DEVICE__
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static inline void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos,
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u8 mask, u8 val)
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#else
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static inline void set_nbcfg_enable_bits_8(struct device *nb_dev, u32 reg_pos,
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u8 mask, u8 val)
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#endif
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{
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u8 reg_old, reg;
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reg = reg_old = pci_read_config8(nb_dev, reg_pos);
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@ -124,8 +179,13 @@ static inline void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask
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}
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}
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static inline void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
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u32 val)
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#ifdef __SIMPLE_DEVICE__
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static inline void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,
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u32 mask, u32 val)
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#else
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static inline void set_nbmc_enable_bits(struct device *nb_dev, u32 reg_pos,
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u32 mask, u32 val)
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#endif
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{
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u32 reg_old, reg;
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reg = reg_old = nbmc_read_index(nb_dev, reg_pos);
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@ -136,7 +196,13 @@ static inline void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
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}
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}
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static inline void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val)
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#ifdef __SIMPLE_DEVICE__
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static inline void set_pcie_enable_bits(pci_devfn_t dev, u32 reg_pos, u32 mask,
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u32 val)
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#else
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static inline void set_pcie_enable_bits(struct device *dev, u32 reg_pos,
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u32 mask, u32 val)
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#endif
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{
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u32 reg_old, reg;
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reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos);
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@ -52,12 +52,16 @@ static const char *me_bios_path_values[] = {
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[ME_DISABLE_BIOS_PATH] = "Disable",
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[ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update",
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};
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static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev);
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static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev);
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#endif
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/* MMIO base address for MEI interface */
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static u32 *mei_base_address;
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void intel_me_mbp_clear(device_t dev);
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#ifdef __SIMPLE_DEVICE__
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void intel_me_mbp_clear(pci_devfn_t dev);
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#else
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void intel_me_mbp_clear(struct device *dev);
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#endif
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#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
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static void mei_dump(void *ptr, int dword, int offset, const char *type)
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@ -112,7 +116,11 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
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mei_dump(ptr, dword, offset, "WRITE");
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}
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static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset)
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#ifdef __SIMPLE_DEVICE__
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static inline void pci_read_dword_ptr(pci_devfn_t dev, void *ptr, int offset)
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#else
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static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)
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#endif
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{
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u32 dword = pci_read_config32(dev, offset);
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memcpy(ptr, &dword, sizeof(dword));
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@ -413,7 +421,11 @@ static inline int mei_sendrecv_mkhi(struct mkhi_header *mkhi,
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* mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read
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* state machine on the BIOS end doesn't match the ME's state machine.
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*/
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static void intel_me_mbp_give_up(device_t dev)
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#ifdef __SIMPLE_DEVICE__
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static void intel_me_mbp_give_up(pci_devfn_t dev)
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#else
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static void intel_me_mbp_give_up(struct device *dev)
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#endif
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{
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struct mei_csr csr;
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@ -429,7 +441,11 @@ static void intel_me_mbp_give_up(device_t dev)
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* mbp clear routine. This will wait for the ME to indicate that
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* the MBP has been read and cleared.
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*/
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void intel_me_mbp_clear(device_t dev)
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#ifdef __SIMPLE_DEVICE__
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void intel_me_mbp_clear(pci_devfn_t dev)
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#else
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void intel_me_mbp_clear(struct device *dev)
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#endif
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{
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int count;
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struct me_hfs2 hfs2;
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@ -657,7 +673,7 @@ static int me_icc_set_clock_enables(u32 mask)
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}
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/* Determine the path that we should take based on ME status */
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static me_bios_path intel_me_path(device_t dev)
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static me_bios_path intel_me_path(struct device *dev)
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{
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me_bios_path path = ME_DISABLE_BIOS_PATH;
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struct me_hfs hfs;
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@ -727,7 +743,7 @@ static me_bios_path intel_me_path(device_t dev)
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}
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/* Prepare ME for MEI messages */
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static int intel_mei_setup(device_t dev)
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static int intel_mei_setup(struct device *dev)
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{
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struct resource *res;
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struct mei_csr host;
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@ -757,7 +773,7 @@ static int intel_mei_setup(device_t dev)
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}
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/* Read the Extend register hash of ME firmware */
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static int intel_me_extend_valid(device_t dev)
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static int intel_me_extend_valid(struct device *dev)
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{
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struct me_heres status;
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u32 extend[8] = {0};
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@ -804,7 +820,7 @@ static int intel_me_extend_valid(device_t dev)
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}
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/* Check whether ME is present and do basic init */
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static void intel_me_init(device_t dev)
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static void intel_me_init(struct device *dev)
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{
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struct southbridge_intel_lynxpoint_config *config = dev->chip_info;
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me_bios_path path = intel_me_path(dev);
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@ -857,7 +873,8 @@ static void intel_me_init(device_t dev)
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*/
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}
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static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
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static void set_subsystem(struct device *dev, unsigned int vendor,
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unsigned int device)
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{
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if (!vendor || !device) {
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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@ -872,7 +889,7 @@ static struct pci_operations pci_ops = {
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.set_subsystem = set_subsystem,
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};
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static void intel_me_enable(device_t dev)
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static void intel_me_enable(struct device *dev)
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{
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/* Avoid talking to the device in S3 path */
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if (acpi_is_wakeup_s3()) {
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@ -939,7 +956,7 @@ struct mbp_payload {
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* mbp seems to be following its own flow, let's retrieve it in a dedicated
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* function.
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*/
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static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev)
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static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev)
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{
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mbp_header mbp_hdr;
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u32 me2host_pending;
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@ -23,14 +23,17 @@
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#include <device/pci_def.h>
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#include "pch.h"
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static device_t pch_get_lpc_device(void)
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#ifdef __SIMPLE_DEVICE__
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static pci_devfn_t pch_get_lpc_device(void)
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{
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#ifdef __SMM__
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return PCI_DEV(0, 0x1f, 0);
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#else
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return dev_find_slot(0, PCI_DEVFN(0x1f, 0));
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#endif
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}
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#else
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static struct device *pch_get_lpc_device(void)
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{
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return dev_find_slot(0, PCI_DEVFN(0x1f, 0));
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}
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#endif
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int pch_silicon_revision(void)
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{
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@ -23,7 +23,11 @@
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typedef struct southbridge_intel_lynxpoint_config config_t;
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static u8 *usb_xhci_mem_base(device_t dev)
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#ifdef __SIMPLE_DEVICE__
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static u8 *usb_xhci_mem_base(pci_devfn_t dev)
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#else
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static u8 *usb_xhci_mem_base(struct device *dev)
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#endif
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{
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u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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@ -34,7 +38,11 @@ static u8 *usb_xhci_mem_base(device_t dev)
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return (u8 *)(mem_base & ~0xf);
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}
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static int usb_xhci_port_count_usb3(device_t dev)
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#ifdef __SIMPLE_DEVICE__
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static int usb_xhci_port_count_usb3(pci_devfn_t dev)
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#else
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static int usb_xhci_port_count_usb3(struct device *dev)
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#endif
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{
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if (pch_is_lp()) {
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/* LynxPoint-LP has 4 SS ports */
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@ -81,7 +89,11 @@ static void usb_xhci_reset_port_usb3(u8 *mem_base, int port)
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* b) Poll for warm reset complete
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* c) Write 1 to port change status bits
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*/
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static void usb_xhci_reset_usb3(device_t dev, int all)
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#ifdef __SIMPLE_DEVICE__
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static void usb_xhci_reset_usb3(pci_devfn_t dev, int all)
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#else
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static void usb_xhci_reset_usb3(struct device *dev, int all)
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#endif
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{
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u32 status, port_disabled;
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int timeout, port;
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