From 1dcf66896dc90edee0dd8eda4d99618f1bc1dcb8 Mon Sep 17 00:00:00 2001 From: Zheng Bao Date: Sat, 9 Oct 2010 02:31:10 +0000 Subject: [PATCH] Trivial. Spell checking. Signed-off-by: Zheng Bao Acked-by: Zheng Bao git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5927 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/amd/amdmct/mct/mct.h | 6 +++--- src/northbridge/amd/amdmct/mct/mct_d.h | 6 +++--- src/northbridge/amd/amdmct/mct/mctardk3.c | 4 ++-- src/northbridge/amd/amdmct/mct/mctardk4.c | 2 +- src/northbridge/amd/amdmct/mct/mctpro_d.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 6 +++--- 6 files changed, 13 insertions(+), 13 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct/mct.h b/src/northbridge/amd/amdmct/mct/mct.h index 5fc3d99b45..e93c0c7dc9 100644 --- a/src/northbridge/amd/amdmct/mct/mct.h +++ b/src/northbridge/amd/amdmct/mct/mct.h @@ -110,7 +110,7 @@ #define Mod64BitMux 4 /* func 2, offset A0h, bit 4 */ #define DisableJitter 1 /* func 2, offset A0h, bit 1 */ #define DramEnabled 9 /* func 2, offset A0h, bit 9 */ -#define SyncOnUcEccEn 2 /* fun 3, offset 44h, bit 2 */ +#define SyncOnUcEccEn 2 /* func 3, offset 44h, bit 2 */ /*============================================================================= Jedec DDR II @@ -349,7 +349,7 @@ struct DCTStatStruc { /* A per Node structure*/ u16 DimmWk2406; /* Bitmap indicating which Dimms have a manufactur's week code <= 24 of 2006 (June)*/ u16 DimmDRPresent; /* Bitmap indicating that Dual Rank Dimms are present*/ u16 DimmPlPresent; /* Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.*/ - u16 ChannelTrainFail; /* Bitmap showing the chanel informaiton about failed Chip Selects*/ + u16 ChannelTrainFail; /* Bitmap showing the channel information about failed Chip Selects*/ /* 0 in any bit field indicates Channel 0*/ /* 1 in any bit field indicates Channel 1*/ }; @@ -509,7 +509,7 @@ struct DCTStatStruc { /* A per Node structure*/ #endif -// global function +/* global function */ u32 NodePresent(u32 Node); u32 Get_NB32n(struct DCTStatStruc *pDCTstat, u32 addrx); u32 Get_NB32(u32 addr); /* NOTE: extend addr to 32 bit for bus > 0 */ diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index 148f987023..2976c8225b 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ b/src/northbridge/amd/amdmct/mct/mct_d.h @@ -236,7 +236,7 @@ #define SPD_MANDATEWK 94 /*Module Manufacturing Week (BCD)*/ /*----------------------------- - Jdec DDR II related equates + Jedec DDR II related equates -----------------------------*/ #define MYEAR06 6 /* Manufacturing Year BCD encoding of 2006 - 06d*/ #define MWEEK24 0x24 /* Manufacturing Week BCD encoding of June - 24d*/ @@ -436,7 +436,7 @@ struct DCTStatStruc { /* A per Node structure*/ u16 DimmWk2406; /* Bitmap indicating which Dimms have a manufactur's week code <= 24 of 2006 (June)*/ u16 DimmDRPresent; /* Bitmap indicating that Dual Rank Dimms are present*/ u16 DimmPlPresent; /* Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.*/ - u16 ChannelTrainFai; /* Bitmap showing the chanel informaiton about failed Chip Selects + u16 ChannelTrainFai; /* Bitmap showing the channel information about failed Chip Selects 0 in any bit field indicates Channel 0 1 in any bit field indicates Channel 1 */ u16 CSUsrTestFail; /* Chip selects excluded by user */ @@ -471,7 +471,7 @@ struct DCTStatStruc { /* A per Node structure*/ u8 MaxDCTs; /* Max number of DCTs in system*/ // NOTE: removed u8 DCT. Use ->dev_ for pci R/W; /*DCT pointer*/ u8 GangedMode; /* Ganged mode enabled, 0 = disabled, 1 = enabled*/ - u8 DRPresent; /* Family 10 present flag, 0 = n0t Fam10, 1 = Fam10*/ + u8 DRPresent; /* Family 10 present flag, 0 = not Fam10, 1 = Fam10*/ u32 NodeSysLimit; /* BASE[39:8],for DCT0+DCT1 system address*/ u8 WrDatGrossH; u8 DqsRcvEnGrossL; diff --git a/src/northbridge/amd/amdmct/mct/mctardk3.c b/src/northbridge/amd/amdmct/mct/mctardk3.c index 7d0ca81fb0..d8e0a78ee9 100644 --- a/src/northbridge/amd/amdmct/mct/mctardk3.c +++ b/src/northbridge/amd/amdmct/mct/mctardk3.c @@ -14,7 +14,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 021100xFF301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ @@ -128,7 +128,7 @@ void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat, * #1, BYTE, Speed (DCTStatstruc.Speed) (Secondary Key) * #2, BYTE, number of Address bus loads on the Channel. (Tershery Key) * These must be listed in ascending order. - * FFh (0xFE) has special meanying of 'any', and must be listed first for each speed grade. + * FFh (0xFE) has special meaning of 'any', and must be listed first for each speed grade. * #3, DWORD, Address Timing Control Register Value * #4, DWORD, Output Driver Compensation Control Register Value * #5, BYTE, Number of DIMMs (Primary Key) diff --git a/src/northbridge/amd/amdmct/mct/mctardk4.c b/src/northbridge/amd/amdmct/mct/mctardk4.c index 9cb2856edb..b57d4cf531 100644 --- a/src/northbridge/amd/amdmct/mct/mctardk4.c +++ b/src/northbridge/amd/amdmct/mct/mctardk4.c @@ -59,7 +59,7 @@ void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat, * #1, BYTE, Speed (DCTStatstruc.Speed) * #2, BYTE, number of Address bus loads on the Channel. * These must be listed in ascending order. - * FFh (-1) has special meanying of 'any', and must be listed first for + * FFh (-1) has special meaning of 'any', and must be listed first for * each speed grade. * #3, DWORD, Address Timing Control Register Value * #4, DWORD, Output Driver Compensation Control Register Value diff --git a/src/northbridge/amd/amdmct/mct/mctpro_d.c b/src/northbridge/amd/amdmct/mct/mctpro_d.c index a2d08d194e..1539a880eb 100644 --- a/src/northbridge/amd/amdmct/mct/mctpro_d.c +++ b/src/northbridge/amd/amdmct/mct/mctpro_d.c @@ -134,7 +134,7 @@ void mct_BeforeDQSTrain_Samp_D(struct MCTStatStruc *pMCTstat, /* Bug#15880: Determine validity of reset settings for DDR PHY timing * regi.. - * Solutiuon: At least, set WrDqs fine delay to be 0 for DDR2 training. + * Solution: At least, set WrDqs fine delay to be 0 for DDR2 training. */ u32 dev; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 0de0a0bd42..a7b6697b75 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -263,7 +263,7 @@ #define SPD_MANDATEWK 94 /*Module Manufacturing Week (BCD)*/ /*----------------------------- - Jdec DDR II related equates + Jedec DDR II related equates -----------------------------*/ #define MYEAR06 6 /* Manufacturing Year BCD encoding of 2006 - 06d*/ #define MWEEK24 0x24 /* Manufacturing Week BCD encoding of June - 24d*/ @@ -464,7 +464,7 @@ struct DCTStatStruc { /* A per Node structure*/ u16 DimmWk2406; /* Bitmap indicating which Dimms have a manufactur's week code <= 24 of 2006 (June)*/ u16 DimmDRPresent; /* Bitmap indicating that Dual Rank Dimms are present*/ u16 DimmPlPresent; /* Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.*/ - u16 ChannelTrainFai; /* Bitmap showing the chanel informaiton about failed Chip Selects + u16 ChannelTrainFai; /* Bitmap showing the channel information about failed Chip Selects 0 in any bit field indicates Channel 0 1 in any bit field indicates Channel 1 */ u16 DIMMTfaw; /* Minimax Tfaw*16 (ns) of DIMMs */ @@ -513,7 +513,7 @@ struct DCTStatStruc { /* A per Node structure*/ u8 MaxDCTs; /* Max number of DCTs in system*/ /* NOTE: removed u8 DCT. Use ->dev_ for pci R/W; */ /*DCT pointer*/ u8 GangedMode; /* Ganged mode enabled, 0 = disabled, 1 = enabled*/ - u8 DRPresent; /* Family 10 present flag, 0 = n0t Fam10, 1 = Fam10*/ + u8 DRPresent; /* Family 10 present flag, 0 = not Fam10, 1 = Fam10*/ u32 NodeSysLimit; /* BASE[39:8],for DCT0+DCT1 system address*/ u8 WrDatGrossH; u8 DqsRcvEnGrossL;