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soc/amd/common/psp: Put spl_fuse in separate compilation unit 

This separates the SPL fusing function into a separate C file which can
be excluded if it is not needed. This allows the psp_set_spl_fuse()
function to be made static again as the state of the function will
always match the boot_state entry.

Move the required #defines to the common header file so they can be
used by both psp_gen2.c & spl_fuse.c.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ifbc774a370dd35a5c1e82f271816e8a036745ad5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73655
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This commit is contained in:
Martin Roth 2023-03-09 10:47:11 -07:00 committed by Felix Held
parent cabf6eaac3
commit 1ddb40f491
4 changed files with 57 additions and 54 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/amd/common/block/psp/Makefile.inc
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@ -29,4 +29,6 @@ ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP) += tpm.c
smm-y += psp_gen2.c smm-y += psp_gen2.c
smm-y += psp_smm_gen2.c smm-y += psp_smm_gen2.c
ramstage-$(CONFIG_HAVE_SPL_FILE) += spl_fuse.c
endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2 endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2

7
src/soc/amd/common/block/psp/psp_def.h
View File

@ -7,6 +7,12 @@
#include <commonlib/helpers.h> #include <commonlib/helpers.h>
#include <amdblocks/psp.h> #include <amdblocks/psp.h>
#define CORE_2_PSP_MSG_38_OFFSET 0x10998 /* 4 byte */
#define CORE_2_PSP_MSG_38_FUSE_SPL BIT(12)
#define CORE_2_PSP_MSG_38_SPL_FUSE_ERROR BIT(13)
#define CORE_2_PSP_MSG_38_SPL_ENTRY_ERROR BIT(14)
#define CORE_2_PSP_MSG_38_SPL_ENTRY_MISSING BIT(15)
/* x86 to PSP commands */ /* x86 to PSP commands */
#define MBOX_BIOS_CMD_SMM_INFO 0x02 #define MBOX_BIOS_CMD_SMM_INFO 0x02
#define MBOX_BIOS_CMD_SX_INFO 0x03 #define MBOX_BIOS_CMD_SX_INFO 0x03
@ -108,6 +114,5 @@ void psp_print_cmd_status(int cmd_status, struct mbox_buffer_header *header);
int send_psp_command(u32 command, void *buffer); int send_psp_command(u32 command, void *buffer);
uint32_t soc_read_c2p38(void); uint32_t soc_read_c2p38(void);
void psp_set_spl_fuse(void *unused);
#endif /* __AMD_PSP_DEF_H__ */ #endif /* __AMD_PSP_DEF_H__ */

53
src/soc/amd/common/block/psp/psp_gen2.c
View File

@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <bootstate.h>
#include <console/console.h>
#include <timer.h> #include <timer.h>
#include <types.h> #include <types.h>
#include <amdblocks/psp.h> #include <amdblocks/psp.h>
@ -12,12 +10,6 @@
#define PSP_MAILBOX_BUFFER_L_OFFSET 0x10574 /* 4 bytes */ #define PSP_MAILBOX_BUFFER_L_OFFSET 0x10574 /* 4 bytes */
#define PSP_MAILBOX_BUFFER_H_OFFSET 0x10578 /* 4 bytes */ #define PSP_MAILBOX_BUFFER_H_OFFSET 0x10578 /* 4 bytes */
#define CORE_2_PSP_MSG_38_OFFSET 0x10998 /* 4 byte */
#define CORE_2_PSP_MSG_38_FUSE_SPL BIT(12)
#define CORE_2_PSP_MSG_38_SPL_FUSE_ERROR BIT(13)
#define CORE_2_PSP_MSG_38_SPL_ENTRY_ERROR BIT(14)
#define CORE_2_PSP_MSG_38_SPL_ENTRY_MISSING BIT(15)
union pspv2_mbox_command { union pspv2_mbox_command {
u32 val; u32 val;
struct pspv2_mbox_cmd_fields { struct pspv2_mbox_cmd_fields {
@ -117,48 +109,3 @@ uint32_t soc_read_c2p38(void)
{ {
return smn_read32(SMN_PSP_PUBLIC_BASE + CORE_2_PSP_MSG_38_OFFSET); return smn_read32(SMN_PSP_PUBLIC_BASE + CORE_2_PSP_MSG_38_OFFSET);
} }
void psp_set_spl_fuse(void *unused)
{
int cmd_status = 0;
struct mbox_cmd_late_spl_buffer buffer = {
.header = {
.size = sizeof(buffer)
}
};
uint32_t c2p38 = soc_read_c2p38();
if (c2p38 & CORE_2_PSP_MSG_38_FUSE_SPL) {
printk(BIOS_DEBUG, "PSP: SPL Fusing may be updated.\n");
} else {
printk(BIOS_DEBUG, "PSP: SPL Fusing not currently required.\n");
return;
}
if (c2p38 & CORE_2_PSP_MSG_38_SPL_FUSE_ERROR) {
printk(BIOS_ERR, "PSP: SPL Table does not meet fuse requirements.\n");
return;
}
if (c2p38 & CORE_2_PSP_MSG_38_SPL_ENTRY_ERROR) {
printk(BIOS_ERR, "PSP: Critical SPL entry missing or current firmware does"
" not meet requirements.\n");
return;
}
if (c2p38 & CORE_2_PSP_MSG_38_SPL_ENTRY_MISSING) {
printk(BIOS_ERR, "PSP: Table of critical SPL values is missing.\n");
return;
}
if (!CONFIG(SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL))
return;
printk(BIOS_DEBUG, "PSP: SPL Fusing Update Requested.\n");
cmd_status = send_psp_command(MBOX_BIOS_CMD_SET_SPL_FUSE, &buffer);
psp_print_cmd_status(cmd_status, NULL);
}
#if CONFIG(HAVE_SPL_FILE)
BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, psp_set_spl_fuse, NULL);
#endif

49
src/soc/amd/common/block/psp/spl_fuse.c Normal file
View File

@ -0,0 +1,49 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootstate.h>
#include <console/console.h>
#include <types.h>
#include "psp_def.h"
static void psp_set_spl_fuse(void *unused)
{
int cmd_status = 0;
struct mbox_cmd_late_spl_buffer buffer = {
.header = {
.size = sizeof(buffer)
}
};
uint32_t c2p38 = soc_read_c2p38();
if (c2p38 & CORE_2_PSP_MSG_38_FUSE_SPL) {
printk(BIOS_DEBUG, "PSP: SPL Fusing may be updated.\n");
} else {
printk(BIOS_DEBUG, "PSP: SPL Fusing not currently required.\n");
return;
}
if (c2p38 & CORE_2_PSP_MSG_38_SPL_FUSE_ERROR) {
printk(BIOS_ERR, "PSP: SPL Table does not meet fuse requirements.\n");
return;
}
if (c2p38 & CORE_2_PSP_MSG_38_SPL_ENTRY_ERROR) {
printk(BIOS_ERR, "PSP: Critical SPL entry missing or current firmware does"
" not meet requirements.\n");
return;
}
if (c2p38 & CORE_2_PSP_MSG_38_SPL_ENTRY_MISSING) {
printk(BIOS_ERR, "PSP: Table of critical SPL values is missing.\n");
return;
}
if (!CONFIG(SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL))
return;
printk(BIOS_DEBUG, "PSP: SPL Fusing Update Requested.\n");
cmd_status = send_psp_command(MBOX_BIOS_CMD_SET_SPL_FUSE, &buffer);
psp_print_cmd_status(cmd_status, NULL);
}
BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, psp_set_spl_fuse, NULL);