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mb/google/brya: Disable unused i2s pins for BT offload 

BT offload hardware design is using only i2s0 pins. Need to disable
i2s2 pins which are not used. As per the hardware spec there is an OR
operation between vgpio and physical gpio pins related to i2s2. During
BT offload configuring the i2s2 pins to its native function is causing
offload issue on proto 2 boards.

BUG=b:201736222
TEST=Verified BT offload on brya on proto 1 and proto 2.

Change-Id: Ifbc53848c6ad12e537216cac3c2871088c094f3d
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This commit is contained in:
Sugnan Prabhu S 2021-10-06 18:42:43 +05:30 committed by Tim Wawrzynczak
parent bd4487c869
commit 1de90868b7
1 changed files with 16 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
src/mainboard/google/brya/variants/brya0/fw_config.c
View File

@ -33,22 +33,28 @@ static const struct pad_config sndw_disable_pads[] = {
PAD_NC(GPP_S5, NONE),
};
static const struct pad_config i2s_enable_pads[] = {
static const struct pad_config i2s0_enable_pads[] = {
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S_HP_SCLK_R */
PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */
PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */
PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */
};
static const struct pad_config i2s2_enable_pads[] = {
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2), /* I2S_SPKR_SCLK_R */
PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), /* I2S_SPKR_SFRM_R */
PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* I2S_PCH_TX_SPKR_RX_R */
PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* I2S_PCH_RX_SPKR_TX */
};
static const struct pad_config i2s_disable_pads[] = {
static const struct pad_config i2s0_disable_pads[] = {
PAD_NC(GPP_R0, NONE),
PAD_NC(GPP_R1, NONE),
PAD_NC(GPP_R2, NONE),
PAD_NC(GPP_R3, NONE),
};
static const struct pad_config i2s2_disable_pads[] = {
PAD_NC(GPP_R4, NONE),
PAD_NC(GPP_R5, NONE),
PAD_NC(GPP_R6, NONE),
@ -80,7 +86,8 @@ static const struct pad_config bt_i2s_disable_pads[] = {
static void enable_i2s(void)
{
gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads));
gpio_configure_pads(i2s0_enable_pads, ARRAY_SIZE(i2s0_enable_pads));
gpio_configure_pads(i2s2_enable_pads, ARRAY_SIZE(i2s2_enable_pads));
gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads));
}
@ -88,7 +95,8 @@ static void fw_config_handle(void *unused)
{
if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) {
printk(BIOS_INFO, "Disable audio related GPIO pins.\n");
gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads));
gpio_configure_pads(i2s0_disable_pads, ARRAY_SIZE(i2s0_disable_pads));
gpio_configure_pads(i2s2_disable_pads, ARRAY_SIZE(i2s2_disable_pads));
gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads));
gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads));
return;
@ -99,11 +107,13 @@ static void fw_config_handle(void *unused)
gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
gpio_configure_pads(sndw_enable_pads, ARRAY_SIZE(sndw_enable_pads));
printk(BIOS_INFO, "BT offload enabled\n");
gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads));
gpio_configure_pads(i2s0_enable_pads, ARRAY_SIZE(i2s0_enable_pads));
gpio_configure_pads(i2s2_disable_pads, ARRAY_SIZE(i2s2_disable_pads));
gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads));
} else {
printk(BIOS_INFO, "BT offload disabled\n");
gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads));
gpio_configure_pads(i2s0_disable_pads, ARRAY_SIZE(i2s0_disable_pads));
gpio_configure_pads(i2s2_disable_pads, ARRAY_SIZE(i2s2_disable_pads));
gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads));
}