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mb/google/zork: modify ELAN TS i2c IRQ to LEVEL active for dirinboz 

EDGE IRQ from TS might be invalid to HOST, configure IRQs
as level triggered to prevent TS lost.

BUG=b:179594439
BRANCH=zork
TEST=1. emerge-zork coreboot chromeos-bootimage
     2. power on, suspend DUT to check TS is functional

Change-Id: Ibbbc73b37932ba1359ffe6f572a15564bb341025
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50416
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kevin Chiu 2021-02-09 12:05:29 +08:00 committed by Martin Roth
parent 6dd2e7b926
commit 1deca23f0a
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/google/zork/variants/dirinboz/overridetree.cb
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@ -120,7 +120,7 @@ chip soc/amd/picasso
register "hid" = ""ELAN0001""
register "desc" = ""ELAN Touchscreen""
register "probed" = "1"
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)"
register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)"
register "enable_delay_ms" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)"