mb/google/volteer: Make devicetree default as Aux Orientation retimer controlled

With new board designs being introduced it does not make sense for the default
devicetree setting to be retimer disabled on port 0 for Aux Orientation.
Change the default to be Aux Orintation retimer controlled on all ports and
move the SOC controlled overrides to the corresponding overridetree files.

BUG=NONE
BRANCH=NONE
TEST=Built image for delbin and verified that port 0 flip is working.

Change-Id: I5ff59493472db096c027d223f2fd61545dc935e2
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
This commit is contained in:
Brandon Breitenstein 2020-08-10 15:02:41 -07:00 committed by Patrick Georgi
parent ad8cf6209f
commit 1df3b70c6a
6 changed files with 20 additions and 3 deletions

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@ -160,9 +160,9 @@ chip soc/intel/tigerlake
# TCSS USB3 # TCSS USB3
register "TcssXhciEn" = "1" register "TcssXhciEn" = "1"
register "TcssAuxOri" = "1" register "TcssAuxOri" = "0"
register "IomTypeCPortPadCfg[0]" = "0x090E000A" register "IomTypeCPortPadCfg[0]" = "0x09000000"
register "IomTypeCPortPadCfg[1]" = "0x090E000D" register "IomTypeCPortPadCfg[1]" = "0x09000000"
register "IomTypeCPortPadCfg[2]" = "0x09000000" register "IomTypeCPortPadCfg[2]" = "0x09000000"
register "IomTypeCPortPadCfg[3]" = "0x09000000" register "IomTypeCPortPadCfg[3]" = "0x09000000"
register "IomTypeCPortPadCfg[4]" = "0x09000000" register "IomTypeCPortPadCfg[4]" = "0x09000000"

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@ -1,5 +1,9 @@
chip soc/intel/tigerlake chip soc/intel/tigerlake
register "TcssAuxOri" = "1"
register "IomTypeCPortPadCfg[0]" = "0x090E000A"
register "IomTypeCPortPadCfg[1]" = "0x090E000D"
device domain 0 on device domain 0 on
end end

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@ -19,6 +19,10 @@ chip soc/intel/tigerlake
register "SaGv" = "SaGv_Disabled" register "SaGv" = "SaGv_Disabled"
register "TcssAuxOri" = "1"
register "IomTypeCPortPadCfg[0]" = "0x090E000A"
register "IomTypeCPortPadCfg[1]" = "0x090E000D"
# I2C Port Config # I2C Port Config
register "SerialIoI2cMode" = "{ register "SerialIoI2cMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C0] = PchSerialIoPci,

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@ -1,5 +1,6 @@
chip soc/intel/tigerlake chip soc/intel/tigerlake
register "SaGv" = "SaGv_Disabled" register "SaGv" = "SaGv_Disabled"
device domain 0 on device domain 0 on
device pci 15.1 on device pci 15.1 on
chip drivers/i2c/hid chip drivers/i2c/hid

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@ -43,6 +43,10 @@ chip soc/intel/tigerlake
}, },
}, },
}" }"
register "TcssAuxOri" = "1"
register "IomTypeCPortPadCfg[0]" = "0x090E000A"
register "IomTypeCPortPadCfg[1]" = "0x090E000D"
device domain 0 on device domain 0 on
device pci 15.0 on device pci 15.0 on
chip drivers/i2c/generic chip drivers/i2c/generic

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@ -1,4 +1,8 @@
chip soc/intel/tigerlake chip soc/intel/tigerlake
register "TcssAuxOri" = "1"
register "IomTypeCPortPadCfg[0]" = "0x090E000A"
register "IomTypeCPortPadCfg[1]" = "0x090E000D"
device domain 0 on device domain 0 on
device pci 15.0 on device pci 15.0 on
chip drivers/i2c/generic chip drivers/i2c/generic