mb/google/volteer: Make devicetree default as Aux Orientation retimer controlled
With new board designs being introduced it does not make sense for the default devicetree setting to be retimer disabled on port 0 for Aux Orientation. Change the default to be Aux Orintation retimer controlled on all ports and move the SOC controlled overrides to the corresponding overridetree files. BUG=NONE BRANCH=NONE TEST=Built image for delbin and verified that port 0 flip is working. Change-Id: I5ff59493472db096c027d223f2fd61545dc935e2 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
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@ -160,9 +160,9 @@ chip soc/intel/tigerlake
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# TCSS USB3
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# TCSS USB3
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register "TcssXhciEn" = "1"
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register "TcssXhciEn" = "1"
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register "TcssAuxOri" = "1"
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register "TcssAuxOri" = "0"
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register "IomTypeCPortPadCfg[0]" = "0x090E000A"
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register "IomTypeCPortPadCfg[0]" = "0x09000000"
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register "IomTypeCPortPadCfg[1]" = "0x090E000D"
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register "IomTypeCPortPadCfg[1]" = "0x09000000"
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register "IomTypeCPortPadCfg[2]" = "0x09000000"
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register "IomTypeCPortPadCfg[2]" = "0x09000000"
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register "IomTypeCPortPadCfg[3]" = "0x09000000"
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register "IomTypeCPortPadCfg[3]" = "0x09000000"
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register "IomTypeCPortPadCfg[4]" = "0x09000000"
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register "IomTypeCPortPadCfg[4]" = "0x09000000"
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@ -1,5 +1,9 @@
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chip soc/intel/tigerlake
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chip soc/intel/tigerlake
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register "TcssAuxOri" = "1"
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register "IomTypeCPortPadCfg[0]" = "0x090E000A"
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register "IomTypeCPortPadCfg[1]" = "0x090E000D"
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device domain 0 on
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device domain 0 on
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end
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end
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@ -19,6 +19,10 @@ chip soc/intel/tigerlake
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register "SaGv" = "SaGv_Disabled"
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register "SaGv" = "SaGv_Disabled"
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register "TcssAuxOri" = "1"
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register "IomTypeCPortPadCfg[0]" = "0x090E000A"
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register "IomTypeCPortPadCfg[1]" = "0x090E000D"
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# I2C Port Config
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# I2C Port Config
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register "SerialIoI2cMode" = "{
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register "SerialIoI2cMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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@ -1,5 +1,6 @@
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chip soc/intel/tigerlake
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chip soc/intel/tigerlake
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register "SaGv" = "SaGv_Disabled"
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register "SaGv" = "SaGv_Disabled"
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device domain 0 on
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device domain 0 on
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device pci 15.1 on
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device pci 15.1 on
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chip drivers/i2c/hid
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chip drivers/i2c/hid
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@ -43,6 +43,10 @@ chip soc/intel/tigerlake
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},
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},
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},
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},
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}"
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}"
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register "TcssAuxOri" = "1"
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register "IomTypeCPortPadCfg[0]" = "0x090E000A"
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register "IomTypeCPortPadCfg[1]" = "0x090E000D"
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device domain 0 on
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device domain 0 on
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device pci 15.0 on
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device pci 15.0 on
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chip drivers/i2c/generic
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chip drivers/i2c/generic
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@ -1,4 +1,8 @@
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chip soc/intel/tigerlake
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chip soc/intel/tigerlake
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register "TcssAuxOri" = "1"
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register "IomTypeCPortPadCfg[0]" = "0x090E000A"
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register "IomTypeCPortPadCfg[1]" = "0x090E000D"
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device domain 0 on
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device domain 0 on
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device pci 15.0 on
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device pci 15.0 on
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chip drivers/i2c/generic
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chip drivers/i2c/generic
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