Get rid of the total impact. Vendor died 5 years ago and nobody cares.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
20d5c2e14e
commit
1df483d3a1
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@ -152,7 +152,7 @@ config USE_FALLBACK_IMAGE
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config HAVE_HARD_RESET
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config HAVE_HARD_RESET
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bool
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bool
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default n
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default 0
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config HAVE_INIT_TIMER
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config HAVE_INIT_TIMER
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bool
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bool
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@ -92,8 +92,6 @@ config VENDOR_TELEVIDEO
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bool "TeleVideo"
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bool "TeleVideo"
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config VENDOR_THOMSON
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config VENDOR_THOMSON
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bool "Thomson"
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bool "Thomson"
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config VENDOR_TOTAL_IMPACT
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bool "Total Impact"
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config VENDOR_TYAN
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config VENDOR_TYAN
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bool "Tyan"
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bool "Tyan"
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config VENDOR_VIA
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config VENDOR_VIA
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@ -321,11 +319,6 @@ config MAINBOARD_VENDOR
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default "Thomson"
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default "Thomson"
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depends on VENDOR_THOMSON
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depends on VENDOR_THOMSON
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config MAINBOARD_VENDOR
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string
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default "Total Impact"
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depends on VENDOR_TOTAL_IMPACT
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config MAINBOARD_VENDOR
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config MAINBOARD_VENDOR
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string
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string
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default "Tyan"
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default "Tyan"
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@ -390,7 +383,6 @@ source "src/mainboard/technexion/Kconfig"
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source "src/mainboard/technologic/Kconfig"
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source "src/mainboard/technologic/Kconfig"
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source "src/mainboard/televideo/Kconfig"
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source "src/mainboard/televideo/Kconfig"
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source "src/mainboard/thomson/Kconfig"
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source "src/mainboard/thomson/Kconfig"
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source "src/mainboard/totalimpact/Kconfig"
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source "src/mainboard/tyan/Kconfig"
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source "src/mainboard/tyan/Kconfig"
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source "src/mainboard/via/Kconfig"
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source "src/mainboard/via/Kconfig"
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@ -1 +0,0 @@
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#
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@ -1,49 +0,0 @@
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##
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## Config file for the Total Impact briQ
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##
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##
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## Early board initialization, called from ppc_main()
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##
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initobject init.o
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initobject clock.o
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##
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## Stage 2 timer support
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##
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object clock.o
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arch ppc end
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if CONFIG_BRIQ_750FX
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dir /cpu/ppc/ppc7xx
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end
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if CONFIG_BRIQ_7400
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dir /cpu/ppc/mpc74xx
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end
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##
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## Include the secondary Configuration files
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##
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chip northbridge/ibm/cpc710
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device pci_domain 0 on # 32bit pci bridge
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device pci 0.0 on
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chip southbridge/winbond/w83c553
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# FIXME The function numbers are ok but the device id is wrong here!
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device pci 0.0 on end # pci to isa bridge
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device pci 0.1 on end # pci ide controller
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end
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end
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end
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device cpu_bus 0 on
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# chip cpu/ppc/ppc7xx
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# device cpu 0 on end
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# end
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end
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end
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##
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## Build the objects we have code for in this directory.
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##
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addaction coreboot.a "$(CONFIG_CROSS_COMPILE)ranlib coreboot.a"
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@ -1,137 +0,0 @@
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##
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## Config file for the Total Impact briQ
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##
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uses CONFIG_TTYS0_DIV
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uses CONFIG_CBFS
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uses CONFIG_ARCH_X86
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uses CONFIG_TTYS0_BASE
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uses CONFIG_BRIQ_750FX
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uses CONFIG_BRIQ_7400
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uses CONFIG_ISA_IO_BASE
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uses CONFIG_ISA_MEM_BASE
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uses CONFIG_PCIC0_CFGADDR
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uses CONFIG_PCIC0_CFGDATA
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uses CONFIG_IO_BASE
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uses CONFIG_HAVE_OPTION_TABLE
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uses CONFIG_COMPRESS
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uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
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uses CONFIG_USE_INIT
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uses CONFIG_NO_POST
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uses CONFIG_CONSOLE_SERIAL8250
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uses CONFIG_IDE_PAYLOAD
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uses CONFIG_COMPRESSED_PAYLOAD_LZMA
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uses CONFIG_PRECOMPRESSED_PAYLOAD
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uses CONFIG_IDE_BOOT_DRIVE
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uses CONFIG_IDE_SWAB CONFIG_IDE_OFFSET
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uses CONFIG_ROM_SIZE
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uses CONFIG_ROM_IMAGE_SIZE
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uses CONFIG_RESET
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uses CONFIG_EXCEPTION_VECTORS
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uses CONFIG_ROMBASE
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uses CONFIG_ROMSTART
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uses CONFIG_RAMBASE
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uses CONFIG_RAMSTART
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uses CONFIG_STACK_SIZE
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uses CONFIG_HEAP_SIZE
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uses CONFIG_BRIQ_750FX
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uses CONFIG_BRIQ_7400
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uses CONFIG_SYS_CLK_FREQ
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uses CONFIG_MAINBOARD
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uses CONFIG_MAINBOARD_VENDOR
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uses CONFIG_MAINBOARD_PART_NUMBER
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uses COREBOOT_EXTRA_VERSION
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uses CONFIG_CROSS_COMPILE
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uses CC
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uses HOSTCC
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uses CONFIG_OBJCOPY
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##
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## Set memory map
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##
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default CONFIG_ISA_IO_BASE=0x80000000
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default CONFIG_ISA_MEM_BASE=0xc0000000
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default CONFIG_PCIC0_CFGADDR=0xff5f8000
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default CONFIG_PCIC0_CFGDATA=0xff5f8010
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default CONFIG_IO_BASE=CONFIG_ISA_IO_BASE
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##
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## The briQ uses weird clocking, 4 = 115200
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##
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default CONFIG_TTYS0_DIV=4
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##
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## Set UART base address
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##
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default CONFIG_TTYS0_BASE=0x3f8
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##
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## The default compiler
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##
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default CC="$(CONFIG_CROSS_COMPILE)gcc"
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default HOSTCC="gcc"
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## use a cross compiler
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#default CONFIG_CROSS_COMPILE="powerpc-eabi-"
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#default CONFIG_CROSS_COMPILE="ppc_74xx-"
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default CONFIG_ARCH_X86=0
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## Use stage 1 initialization code
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default CONFIG_USE_INIT=1
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## We don't use compressed image
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default CONFIG_COMPRESS=0
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## Turn off POST codes
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default CONFIG_NO_POST=1
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## Enable serial console
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default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
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default CONFIG_CONSOLE_SERIAL8250=1
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## Boot linux from IDE
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default CONFIG_IDE_PAYLOAD=1
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default CONFIG_IDE_BOOT_DRIVE=0
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default CONFIG_IDE_SWAB=1
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default CONFIG_IDE_OFFSET=0
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# ROM is 1Mb
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default CONFIG_ROM_SIZE=1048576
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default CONFIG_ROM_IMAGE_SIZE=128*1024
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# Set stack and heap sizes (stage 2)
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default CONFIG_STACK_SIZE=0x10000
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default CONFIG_HEAP_SIZE=0x10000
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##
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## System clock
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##
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default CONFIG_SYS_CLK_FREQ=33
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# Sandpoint Demo Board
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## Base of ROM
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default CONFIG_ROMBASE=0xfff00000
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## Sandpoint reset vector
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default CONFIG_RESET=CONFIG_ROMBASE+0x100
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## Exception vectors (other than reset vector)
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default CONFIG_EXCEPTION_VECTORS=CONFIG_RESET+0x100
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## Start of coreboot in the boot rom
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## = CONFIG_RESET + exeception vector table size
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default CONFIG_ROMSTART=CONFIG_RESET+0x3100
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## Coreboot C code runs at this location in RAM
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default CONFIG_RAMBASE=0x00100000
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default CONFIG_RAMSTART=0x00100000
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default CONFIG_BRIQ_750FX=1
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#default CONFIG_BRIQ_7400=1
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### End Options.lb
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#
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# CBFS
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#
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#
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default CONFIG_CBFS=1
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end
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@ -1,178 +0,0 @@
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; bdiGDB configuration file for briQ (http://www.totalimpact.com)
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; ---------------------------------------------------------------
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;
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; NOTE: As of June 2004, you will need to install a pull-down
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; on the COP/JTAG QACK line. Without this, the BDI2000
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; is not able to halt the CPU
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; (http://www.ultsol.com/faq-P210.htm)
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;
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[INIT]
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; init core register
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WREG MSR 0x00000000 ;clear MSR
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;
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; init CPC710
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;
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WM32 0xFF000010 0xF0000000 ; RSTR
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WM32 0xFF001020 0x00000000 ; SIOC
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WM32 0xFF001000 0x00780000 ; UCTL (resID=7|TBE)
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WM32 0xFF001030 0x00000000 ; ABCNTL
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WM32 0xFF001040 0x00000000 ; SRST
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WM32 0xFF001050 0x00000000 ; ERRC
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WM32 0xFF001060 0x00000000 ; SESR
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WM32 0xFF001070 0x00000000 ; SEAR
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WM32 0xFF001100 0x000000E0 ; PGCHP (PReP|ARTRY|750|SYS_TEA)
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WM32 0xFF001130 0x40000000 ; GPDIR
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WM32 0xFF001150 0x40000000 ; GPOUT
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WM32 0xFF001160 0x709C2508 ; ATAS
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WM32 0xFF001170 0x00000000 ; AVDG
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WM32 0xFF001220 0x00000000 ; MESR
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WM32 0xFF001230 0x00000000 ; MEAR
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WM32 0xFF001210 0x00000000 ; MWPR
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WM32 0xFF001120 0x00000000 ; RGBAN1
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;
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; init memory - this assumes 2 x 512MB DIMMs
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;
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WM32 0xFF001300 0x80000080 ; MCER0
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WM32 0xFF001310 0x82000080 ; MCER1
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WM32 0xFF001320 0x00000000 ; MCER2
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WM32 0xFF001330 0x00000000 ; MCER3
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WM32 0xFF001340 0x00000000 ; MCER4
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WM32 0xFF001350 0x00000000 ; MCER5
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WM32 0xFF001200 0xD2B06000 ; MCCR
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DELAY 1000
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;
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; enable pci
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;
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WM32 0xFF00000C 0x80000002 ; CNFR
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WM32 0xFF200018 0xFF500000 ; PCIBAR
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WM32 0xFF201000 0x80000000 ; PCIENB
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WM32 0xFF00000C 0x00000000 ; CNFR
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;
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; config pci
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;
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WM32 0xFF5F8000 0x06000080
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WM16 0xFF5F8010 0xFFFF
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WM32 0xFF5F8000 0x40000080
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WM16 0xFF5F8010 0x0000
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WM32 0xFF5F6120 0x40000000 ; PCIDG
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WM32 0xFF5F7800 0x00000000 ; PIBAR
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WM32 0xFF5F7810 0x00000000 ; PMBAR
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WM32 0xFF5F7F20 0xA000C000 ; PR
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WM32 0xFF5F7F30 0xFC000000 ; ACR
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WM32 0xFF5F7F40 0xF8000000 ; MSIZE
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WM32 0xFF5F7F60 0xF8000000 ; IOSIZE
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WM32 0xFF5F7F80 0xC0000000 ; SMBAR
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WM32 0xFF5F7FC0 0x80000000 ; SIBAR
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WM32 0xFF5F8100 0x00000080 ; PSSIZE
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WM32 0xFF5F8120 0x00000000 ; BARPS
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WM32 0xFF5F8140 0x00000080 ; PSBAR
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WM32 0xFF5F8200 0x00000000 ; BPMDLK
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WM32 0xFF5F8210 0x00000000 ; TPMDLK
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WM32 0xFF5F8220 0x00000000 ; BIODLK
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WM32 0xFF5F8230 0x00000000 ; TIODLK
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WM32 0xFF5F8000 0x04000080
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WM16 0xFF5F8010 0xA7FD
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WM32 0xFF5F7EF0 0xFC000000 ; CRR
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;
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; VFD - output the sequence '01234' to show
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; something is happening
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;
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;WM8 0x80000390 0x38
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;WM8 0x80000390 0x01
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;WM8 0x80000390 0x0C
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;WM8 0x80000390 0x06
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;WM8 0x80000390 0x02
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;DELAY 100
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;WM8 0x80000391 0x30
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;DELAY 100
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;WM8 0x80000391 0x31
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;DELAY 100
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;WM8 0x80000391 0x32
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;DELAY 100
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;WM8 0x80000391 0x33
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;DELAY 100
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;WM8 0x80000391 0x34
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;
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; UART - output the sequence '01234' to show
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; something is happening
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;
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WM8 0x800003F9 0
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WM8 0x800003FA 1
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WM8 0x800003FB 0x83
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WM8 0x800003F8 4 ; 115200
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WM8 0x800003F9 0
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WM8 0x800003FB 0x3
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DELAY 100
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WM8 0x800003F8 0x30
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DELAY 100
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WM8 0x800003F8 0x31
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DELAY 100
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WM8 0x800003F8 0x32
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DELAY 100
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WM8 0x800003F8 0x33
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DELAY 100
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WM8 0x800003F8 0x34
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;
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; define maximal transfer size
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;TSZ1 0xFF800000 0xFFFFFFFF ;ROM space (only for PCI boot ROM)
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TSZ4 0xFF800000 0xFFFFFFFF ;ROM space (only for Local bus flash)
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[TARGET]
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CPUTYPE 7400 ;the CPU type (603EV,750,8240,8260,7400)
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JTAGCLOCK 0 ;use 16 MHz JTAG clock
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WORKSPACE 0x00000000 ;workspace in target RAM for data cache flush
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BDIMODE AGENT ;the BDI working mode (LOADONLY | AGENT | GATEWAY)
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BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint
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STEPMODE TRACE ;TRACE or HWBP, HWPB uses a hardware breakpoint
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;VECTOR CATCH ;catch unhandled exceptions
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DCACHE FLUSH ;data cache flushing (FLUSH | NOFLUSH)
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;PARITY ON ;enable data parity generation
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;MEMDELAY 4000 ;additional memory access delay
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;REGLIST STD ;select register to transfer to GDB
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;L2PM 0x00100000 0x80000 ;L2 privat memory
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BOOTADDR 0xfff00100
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STARTUP RESET
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[HOST]
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FORMAT ELF
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LOAD MANUAL ;load code MANUAL or AUTO after reset
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DEBUGPORT 2001
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[FLASH]
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; Am29LV800BB on local processor bus (RCS0)
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; set PPMC7410 switch SW2-1 OFF => ROM on Local bus
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; enable flash write in PICR1 (see INIT part)
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; set maximal transfer size to 4 bytes (see INIT part)
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||||||
CHIPTYPE AM29F ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16)
|
|
||||||
CHIPSIZE 0x100000 ;The size of one flash chip in bytes (e.g. Am29LV800BB = 0x100000)
|
|
||||||
BUSWIDTH 8 ;The width of the flash memory bus in bits (8 | 16 | 32 | 64)
|
|
||||||
;WORKSPACE 0x00000000 ;workspace in SDRAM
|
|
||||||
FILE coreboot.rom
|
|
||||||
FORMAT ELF
|
|
||||||
ERASE 0xFFF00000 ;erase sector 0 of flash
|
|
||||||
ERASE 0xFFF10000 ;erase sector 1 of flash
|
|
||||||
ERASE 0xFFF20000 ;erase sector 2 of flash
|
|
||||||
ERASE 0xFFF30000 ;erase sector 3 of flash
|
|
||||||
ERASE 0xFFF40000 ;erase sector 4 of flash
|
|
||||||
ERASE 0xFFF50000 ;erase sector 5 of flash
|
|
||||||
ERASE 0xFFF60000 ;erase sector 6 of flash
|
|
||||||
ERASE 0xFFF70000 ;erase sector 7 of flash
|
|
||||||
;ERASE 0xFFF80000 ;erase sector 8 of flash
|
|
||||||
;ERASE 0xFFF90000 ;erase sector 9 of flash
|
|
||||||
;ERASE 0xFFFA0000 ;erase sector 10 of flash
|
|
||||||
;ERASE 0xFFFB0000 ;erase sector 11 of flash
|
|
||||||
;ERASE 0xFFFC0000 ;erase sector 12 of flash
|
|
||||||
;ERASE 0xFFFD0000 ;erase sector 13 of flash
|
|
||||||
;ERASE 0xFFFE0000 ;erase sector 14 of flash
|
|
||||||
;ERASE 0xFFFF0000 ;erase sector 15 of flash
|
|
||||||
|
|
||||||
[REGS]
|
|
||||||
;DMM1 0xFC000000 ;Embedded utility memory base address
|
|
||||||
;IMM1 0xFEC00000 0xFEE00000 ;configuration registers at byte offset 0
|
|
||||||
;IMM2 0xFEC00000 0xFEE00001 ;configuration registers at byte offset 1
|
|
||||||
;IMM3 0xFEC00000 0xFEE00002 ;configuration registers at byte offset 2
|
|
||||||
;IMM4 0xFEC00000 0xFEE00003 ;configuration registers at byte offset 3
|
|
||||||
FILE cpc700.def
|
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -1,42 +0,0 @@
|
||||||
#include <stdint.h>
|
|
||||||
#include "../../../northbridge/ibm/cpc710/cpc710.h"
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Bus clock jumper settings on SIOR0 27:28
|
|
||||||
*/
|
|
||||||
static uint32_t BusClockSpeed[] = {
|
|
||||||
66000000, /* 00 */
|
|
||||||
83000000, /* 01 */
|
|
||||||
100000000, /* 10 */
|
|
||||||
133000000 /* 11 */
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Timer frequency is 1/4 of the bus clock frequency.
|
|
||||||
*
|
|
||||||
* For the briQ, bits 27:28 of SIOR0 encode bus clock frequency.
|
|
||||||
*/
|
|
||||||
unsigned long
|
|
||||||
get_timer_freq(void)
|
|
||||||
{
|
|
||||||
uint32_t sior0 = getCPC710(CPC710_SDRAM0_SIOR0);
|
|
||||||
|
|
||||||
return BusClockSpeed[(sior0 >> 3) & 0x2] / 4;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Frequency of PCI bus.
|
|
||||||
*
|
|
||||||
* For the briQ, bit 29 of SIOR0 is 66MHz enable (active low).
|
|
||||||
*/
|
|
||||||
unsigned long
|
|
||||||
get_pci_bus_freq(void)
|
|
||||||
{
|
|
||||||
uint32_t sior0 = getCPC710(CPC710_SDRAM0_SIOR0);
|
|
||||||
|
|
||||||
if (sior0 & 0x4 == 0x4)
|
|
||||||
return 33000000;
|
|
||||||
|
|
||||||
return 66000000;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
@ -1,22 +0,0 @@
|
||||||
chip northbridge/ibm/cpc710
|
|
||||||
device pci_domain 0 on # 32bit pci bridge
|
|
||||||
device pci 0.0 on
|
|
||||||
chip southbridge/winbond/w83c553
|
|
||||||
# FIXME The function numbers are ok but the device id is wrong here!
|
|
||||||
device pci 0.0 on end # pci to isa bridge
|
|
||||||
device pci 0.1 on end # pci ide controller
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
device cpu_bus 0 on
|
|
||||||
# chip cpu/ppc/ppc7xx
|
|
||||||
# device cpu 0 on end
|
|
||||||
# end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
##
|
|
||||||
## Build the objects we have code for in this directory.
|
|
||||||
##
|
|
||||||
|
|
||||||
addaction coreboot.a "$(CONFIG_CROSS_COMPILE)ranlib coreboot.a"
|
|
||||||
|
|
@ -1,47 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (C) 2003, Greg Watson <gwatson@lanl.gov>
|
|
||||||
*
|
|
||||||
* See file CREDITS for list of people who contributed to this
|
|
||||||
* project.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or
|
|
||||||
* modify it under the terms of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation; either version 2 of
|
|
||||||
* the License, or (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
|
||||||
* MA 02110-1301 USA
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Do very early board initialization:
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <ppc_asm.tmpl>
|
|
||||||
#include <ppc.h>
|
|
||||||
#include <arch/io.h>
|
|
||||||
#include <console/console.h>
|
|
||||||
#include <uart8250.h>
|
|
||||||
|
|
||||||
void
|
|
||||||
board_init(void)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
|
|
||||||
void
|
|
||||||
board_init2(void)
|
|
||||||
{
|
|
||||||
/*
|
|
||||||
* Enable UART
|
|
||||||
*/
|
|
||||||
uart8250_init(CONFIG_TTYS0_BASE, CONFIG_TTYS0_DIV, CONFIG_TTYS0_LCS);
|
|
||||||
printk_info("briQ initialized...\n");
|
|
||||||
|
|
||||||
}
|
|
||||||
Loading…
Reference in New Issue