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Implemented workaround for erratum 169, obsoleting erratum 131. 

Workaround for 131 removed.
Changed workaround for erratum 110 to only include pre-revision-F
processors.

For details, check AMD publications:
#25759 (Errata for Fam F pre-revision F processors)
#33610 (Errata for Fam F revision F and later processor)

Based on work and previous patches by:
Rudolf Marek <r.marek@assembler.cz> 
Josef Kellermann <seppk@arcor.de>

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6340 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Alexandru Gagniuc 2011-02-10 07:51:51 +00:00 committed by Patrick Georgi
parent 31e0deac0e
commit 1df854248b
2 changed files with 37 additions and 15 deletions
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36
src/cpu/amd/model_fxx/model_fxx_init.c
View File

@ -411,33 +411,35 @@ static inline void k8_errata(void)
msr.hi |= 1 << (43 - 32);
wrmsr_amd(BU_CFG_MSR, msr);
/* Erratum 110 */
/* This erratum applies to D0 thru E6 revisions
* Revision F and later are unaffected. There are two fixes
* depending on processor revision.
*/
if (is_cpu_d0()) {
/* Erratum 110 ... */
msr = rdmsr_amd(CPU_ID_HYPER_EXT_FEATURES);
msr.hi |= 1;
wrmsr_amd(CPU_ID_HYPER_EXT_FEATURES, msr);
}
#endif
#if CONFIG_K8_REV_F_SUPPORT == 0
if (!is_cpu_pre_e0())
#endif
{
/* Erratum 110 ... */
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
msr.hi |= 1;
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
}
#endif
#if CONFIG_K8_REV_F_SUPPORT == 0
/* I can't touch this msr on early buggy cpus */
/* I can't touch this msr on early buggy cpus */
if (!is_cpu_pre_b3())
#endif
{
/* Erratum 89 ... */
msr = rdmsr(NB_CFG_MSR);
msr.lo |= 1 << 3;
#if CONFIG_K8_REV_F_SUPPORT == 0
if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
/* D0 later don't need it */
@ -448,6 +450,18 @@ static inline void k8_errata(void)
msr.hi |= 1 << (36 - 32);
}
#endif
/* Erratum 89 ... */
/* Erratum 89 is mistakenly labeled as 88 in AMD pub #25759
* It is correctly labeled as 89 on page 49 of the document
* and in AMD pub#33610
*/
msr.lo |= 1 << 3;
/* Erratum 169 */
/* This supersedes erratum 131; 131 should not be applied with 169
* We also need to set some bits in the northbridge, handled in src/northbridge/amdk8/
*/
msr.hi |= 1;
wrmsr(NB_CFG_MSR, msr);
}
/* Erratum 122 */
@ -455,12 +469,6 @@ static inline void k8_errata(void)
msr.lo |= 1 << 6;
wrmsr(HWCR_MSR, msr);
#if CONFIG_K8_REV_F_SUPPORT == 1
/* Erratum 131... */
msr = rdmsr(NB_CFG_MSR);
msr.lo |= 1 << 20;
wrmsr(NB_CFG_MSR, msr);
#endif
}

16
src/northbridge/amd/amdk8/coherent_ht.c
View File

@ -1662,10 +1662,10 @@ static int apply_cpu_errata_fixes(unsigned nodes)
unsigned node;
int needs_reset = 0;
for(node = 0; node < nodes; node++) {
#if CONFIG_K8_REV_F_SUPPORT == 0
device_t dev;
uint32_t cmd;
dev = NODE_MC(node);
#if CONFIG_K8_REV_F_SUPPORT == 0
if (is_cpu_pre_c0()) {
/* Errata 66
@ -1708,6 +1708,20 @@ static int apply_cpu_errata_fixes(unsigned nodes)
}
}
#endif
#if CONFIG_K8_REV_F_SUPPORT == 0
/* I can't touch this msr on early buggy cpus, and cannot apply either 169 or 131 */
if (!is_cpu_pre_b3())
#endif
{
/* Errata 169 */
/* We also need to set some bits in NB_CFG_MSR, which is handled in src/cpu/amd/model_fxx/ */
cmd = pci_read_config32(dev, 0x68);
cmd &= ~(1 << 22);
cmd |= (1 << 21);
pci_write_config32(dev, 0x68, cmd);
}
}
return needs_reset;
}