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sb/intel/*: Delete invalid comment 

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Change-Id: I3de04b8c03f7c511376dec922a60958ffc3bf6a3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Angel Pons 2020-07-22 00:30:56 +02:00
parent 1ba6201518
commit 1e1515fc9d
2 changed files with 0 additions and 2 deletions
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1
src/southbridge/intel/i82801gx/early_init.c
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@ -66,7 +66,6 @@ void i82801gx_early_init(void)
enable_smbus(); enable_smbus();
/* Setting up Southbridge. In the northbridge code. */
printk(BIOS_DEBUG, "Setting up static southbridge registers..."); printk(BIOS_DEBUG, "Setting up static southbridge registers...");
i82801gx_setup_bars(); i82801gx_setup_bars();

1
src/southbridge/intel/lynxpoint/early_pch.c
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@ -41,7 +41,6 @@ int pch_is_lp(void)
static void pch_enable_bars(void) static void pch_enable_bars(void)
{ {
/* Setting up Southbridge. In the northbridge code. */
pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1);