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lib/prog_loaders: Allow platforms to skip stage cache 

Before multi-CBFS support was added, x86 platforms cached their
ramstage in TSEG so that it could be re-used on the resume
path. However, more resources/assets are being put in cbfs that are
utilized during ramstage. Just caching ramstage does not mean that
correct cbfs region is used for all the data. Thus, provide an option
to allow platforms to skip caching any component for resume.

Change-Id: I0e957a6b859cc7d700aaff67209a17c6558be5de
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14636
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Furquan Shaikh 2016-05-06 09:20:35 -07:00
parent 94b18a1757
commit 1e162bf8bd
3 changed files with 20 additions and 4 deletions
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7
src/Kconfig
View File

@ -262,6 +262,13 @@ config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
The relocated ramstage is saved in an area specified by the
by the board and/or chipset.
config NO_STAGE_CACHE
bool
default n
help
Do not save any component in stage cache for resume path. On resume,
all components would be read back from CBFS again.
config FLASHMAP_OFFSET
hex "Flash Map Offset"
default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE

8
src/drivers/intel/fsp1_1/ramstage.c
View File

@ -158,6 +158,11 @@ static void fsp_cache_save(struct prog *fsp)
if (IS_ENABLED(CONFIG_DISPLAY_SMM_MEMORY_MAP))
smm_memory_map();
if (IS_ENABLED(CONFIG_NO_STAGE_CACHE))
return;
printk(BIOS_DEBUG, "FSP: Saving binary in cache\n");
if (prog_entry(fsp) == NULL) {
printk(BIOS_ERR, "ERROR: No FSP to save in cache.\n");
return;
@ -186,12 +191,11 @@ void intel_silicon_init(void)
struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin");
int is_s3_wakeup = acpi_is_wakeup_s3();
if (is_s3_wakeup) {
if (is_s3_wakeup && !IS_ENABLED(CONFIG_NO_STAGE_CACHE)) {
printk(BIOS_DEBUG, "FSP: Loading binary from cache\n");
stage_cache_load_stage(STAGE_REFCODE, &fsp);
} else {
fsp_find_and_relocate(&fsp);
printk(BIOS_DEBUG, "FSP: Saving binary in cache\n");
fsp_cache_save(&fsp);
}

9
src/lib/prog_loaders.c
View File

@ -107,8 +107,13 @@ void run_ramstage(void)
timestamp_add_now(TS_END_ROMSTAGE);
/* Only x86 systems currently take the same firmware path on resume. */
if (IS_ENABLED(CONFIG_ARCH_X86) && IS_ENABLED(CONFIG_EARLY_CBMEM_INIT))
/*
* Only x86 systems using ramstage stage cache currently take the same
* firmware path on resume.
*/
if (IS_ENABLED(CONFIG_ARCH_X86) &&
!IS_ENABLED(CONFIG_NO_STAGE_CACHE) &&
IS_ENABLED(CONFIG_EARLY_CBMEM_INIT))
run_ramstage_from_resume(romstage_handoff_find_or_add(),
&ramstage);