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southbridge/amd/sb600: Update HPET base address with #define 

The SB600 code had the base address of the HPET hardcoded throughout.
It looks like the plan was to have it be updated in ACPI if needed,
but this wasn't ever implemented.  The variable names being used to
do this update were the same, causing an IASL warning.  Because of
this, the operation to update the HPET address actually did nothing.
This was fine, because it didn't actually need to be updated.

- Replace all that code with a #define.
- Add and update some comments in the same area.

Fixes IASL warning:
dsdt.aml   1505:       Store(HPBA, HPBA)
Warning  3023 -                      ^ Duplicate value in list (Source is the
same as Target)

Change-Id: I9ba5fe226a4a464e0045ce7d3406898760df5e5a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12705
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
This commit is contained in:
Martin Roth 2015-12-10 08:19:27 -07:00
parent 49bbfcd5d3
commit 1e1c7ac3b4
8 changed files with 41 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
src/mainboard/amd/dbm690t/dsdt.asl
View File

@ -13,6 +13,8 @@
* GNU General Public License for more details.
*/
#include <southbridge/amd/sb600/sb600.h>
/* DefinitionBlock Statement */
DefinitionBlock (
"DSDT.AML", /* Output filename */
@ -33,7 +35,6 @@ DefinitionBlock (
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
@ -1361,20 +1362,18 @@ DefinitionBlock (
})
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
Device(HPTM) {
Device(HPTM) { /* HPET */
Name(_HID,EISAID("PNP0103"))
Name(CRS,ResourceTemplate() {
Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x00000400, HPT) /* 1kb reserved space */
})
Method(_STA, 0) {
Return(0x0F) /* sata is visible */
Return(0x0F) /* HPET is visible */
}
Method(_CRS, 0) {
CreateDwordField(CRS, ^HPT._BAS, HPBA)
Store(HPBA, HPBA)
Return(CRS)
}
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
} /* End Device(_SB.PCI0.LpcIsaBr.HPTM) */
} /* end LIBR */
Device(HPBR) {

13
src/mainboard/amd/pistachio/dsdt.asl
View File

@ -13,6 +13,8 @@
* GNU General Public License for more details.
*/
#include <southbridge/amd/sb600/sb600.h>
/* DefinitionBlock Statement */
DefinitionBlock (
"DSDT.AML", /* Output filename */
@ -33,7 +35,6 @@ DefinitionBlock (
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
@ -1360,20 +1361,18 @@ DefinitionBlock (
})
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
Device(HPTM) {
Device(HPTM) { /* HPET */
Name(_HID,EISAID("PNP0103"))
Name(CRS,ResourceTemplate() {
Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x00000400, HPT) /* 1kb reserved space */
})
Method(_STA, 0) {
Return(0x0F) /* sata is visible */
Return(0x0F) /* HPET is visible */
}
Method(_CRS, 0) {
CreateDwordField(CRS, ^HPT._BAS, HPBA)
Store(HPBA, HPBA)
Return(CRS)
}
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
} /* End Device(_SB.PCI0.LpcIsaBr.HPTM) */
} /* end LIBR */
Device(HPBR) {

13
src/mainboard/kontron/kt690/dsdt.asl
View File

@ -13,6 +13,8 @@
* GNU General Public License for more details.
*/
#include <southbridge/amd/sb600/sb600.h>
/* DefinitionBlock Statement */
DefinitionBlock (
"dsdt.aml", /* Output filename */
@ -33,7 +35,6 @@ DefinitionBlock (
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
@ -1362,20 +1363,18 @@ DefinitionBlock (
})
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
Device(HPTM) {
Device(HPTM) { /* HPET */
Name(_HID,EISAID("PNP0103"))
Name(CRS,ResourceTemplate() {
Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x00000400, HPT) /* 1kb reserved space */
})
Method(_STA, 0) {
Return(0x0F) /* sata is visible */
Return(0x0F) /* HPET is visible */
}
Method(_CRS, 0) {
CreateDwordField(CRS, ^HPT._BAS, HPBA)
Store(HPBA, HPBA)
Return(CRS)
}
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
} /* End Device(_SB.PCI0.LpcIsaBr.HPTM) */
} /* end LIBR */
Device(HPBR) {

10
src/mainboard/siemens/sitemp_g1p1/dsdt.asl
View File

@ -16,13 +16,13 @@
*/
#include <arch/ioapic.h>
#include <cpu/x86/lapic_def.h>
#include <southbridge/amd/sb600/sb600.h>
DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
{
/* Data to be patched by the BIOS during POST */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
/* USB overcurrent mapping pins. */
Name(UOM0, 0)
@ -1004,17 +1004,15 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
})
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
Device(HPET) {
Device(HPET) { /* HPET */
Name(_HID,EISAID("PNP0103"))
Name(CRS,ResourceTemplate() {
Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x00000400, HPT) /* 1kb reserved space */
})
Method(_STA, 0) {
Return(0x0F) /* sata is visible */
Return(0x0F) /* HPET is visible */
}
Method(_CRS, 0) {
CreateDwordField(CRS, ^HPT._BAS, HPBA)
Store(HPBA, HPBA)
Return(CRS)
}
}

13
src/mainboard/technexion/tim5690/dsdt.asl
View File

@ -13,6 +13,8 @@
* GNU General Public License for more details.
*/
#include <southbridge/amd/sb600/sb600.h>
/* DefinitionBlock Statement */
DefinitionBlock (
"DSDT.AML", /* Output filename */
@ -33,7 +35,6 @@ DefinitionBlock (
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
@ -1361,20 +1362,18 @@ DefinitionBlock (
})
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
Device(HPTM) {
Device(HPTM) { /* HPET */
Name(_HID,EISAID("PNP0103"))
Name(CRS,ResourceTemplate() {
Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x00000400, HPT) /* 1kb reserved space */
})
Method(_STA, 0) {
Return(0x0F) /* sata is visible */
Return(0x0F) /* HPET is visible */
}
Method(_CRS, 0) {
CreateDwordField(CRS, ^HPT._BAS, HPBA)
Store(HPBA, HPBA)
Return(CRS)
}
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
} /* End Device(_SB.PCI0.LpcIsaBr.HPTM) */
} /* end LIBR */
Device(HPBR) {

13
src/mainboard/technexion/tim8690/dsdt.asl
View File

@ -13,6 +13,8 @@
* GNU General Public License for more details.
*/
#include <southbridge/amd/sb600/sb600.h>
/* DefinitionBlock Statement */
DefinitionBlock (
"DSDT.AML", /* Output filename */
@ -33,7 +35,6 @@ DefinitionBlock (
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
@ -1361,20 +1362,18 @@ DefinitionBlock (
})
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
Device(HPTM) {
Device(HPTM) { /* HPET */
Name(_HID,EISAID("PNP0103"))
Name(CRS,ResourceTemplate() {
Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x00000400, HPT) /* 1kb reserved space */
})
Method(_STA, 0) {
Return(0x0F) /* sata is visible */
Return(0x0F) /* HPET is visible */
}
Method(_CRS, 0) {
CreateDwordField(CRS, ^HPT._BAS, HPBA)
Store(HPBA, HPBA)
Return(CRS)
}
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
} /* End Device(_SB.PCI0.LpcIsaBr.HPTM) */
} /* end LIBR */
Device(HPBR) {

6
src/southbridge/amd/sb600/sb600.h
View File

@ -16,8 +16,10 @@
#ifndef SB600_H
#define SB600_H
#ifndef __ACPI__
#include <device/pci_ids.h>
#include "chip.h"
#endif
/* Power management index/data registers */
#define PM_INDEX 0xcd6
@ -25,6 +27,9 @@
#define PM2_INDEX 0xcd0
#define PM2_DATA 0xcd1
#define HPET_BASE_ADDRESS 0xfed00000
#ifndef __ACPI__
extern void pm_iowrite(u8 reg, u8 value);
extern u8 pm_ioread(u8 reg);
extern void pm2_iowrite(u8 reg, u8 value);
@ -36,4 +41,5 @@ void sb600_enable(device_t dev);
void sb600_lpc_port80(void);
void sb600_pci_port80(void);
#endif /* __ACPI__ */
#endif /* SB600_H */

2
src/southbridge/amd/sb600/sm.c
View File

@ -305,7 +305,7 @@ static void sb600_sm_read_resources(device_t dev)
res->flags = IORESOURCE_MEM | IORESOURCE_FIXED;
res = new_resource(dev, 0x14); /* hpet */
res->base = 0xfed00000; /* reset hpet to widely accepted address */
res->base = HPET_BASE_ADDRESS; /* reset hpet to widely accepted address */
res->size = 0x400;
res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */
res->align = 8;