diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
index 3bb802ec78..67d35b396f 100644
--- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
+++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
@@ -113,7 +113,7 @@ chip soc/intel/cannonlake
 		device pci 16.4 off	end	# Management Engine Interface 3
 		device pci 16.5 off	end	# Management Engine Interface 4
 		device pci 17.0 on		# SATA
-			register "SataMode" = "Sata_AHCI"
+			register "SataMode" = "SATA_AHCI"
 			register "SataSalpSupport" = "1"
 			# Port 2 (J_SSD2)
 			register "SataPortsEnable[1]" = "1"
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index 31f6652401..5826f79ba9 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -20,7 +20,7 @@ chip soc/intel/cannonlake
 	# FSP configuration
 	register "SkipExtGfxScan" = "1"
 	register "SataSalpSupport" = "1"
-	register "SataMode" = "Sata_AHCI"
+	register "SataMode" = "SATA_AHCI"
 	register "SataPortsEnable[1]" = "1"
 	register "SataPortsDevSlp[1]" = "1"
 	# Configure devslp pad reset to PLT_RST
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index 9e05213440..69e4e7d059 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -16,7 +16,7 @@ chip soc/intel/cannonlake
 	# FSP configuration
 	register "SaGv" = "SaGv_Enabled"
 	register "SataSalpSupport" = "1"
-	register "SataMode" = "Sata_AHCI"
+	register "SataMode" = "SATA_AHCI"
 	register "SataPortsEnable[2]" = "1"
 	register "SataPortsDevSlp[2]" = "1"
 	register "SkipExtGfxScan" = "1"
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 005a783e4f..021feba777 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -16,7 +16,7 @@ chip soc/intel/cannonlake
 	# FSP configuration
 	register "SaGv" = "SaGv_Enabled"
 	register "SataSalpSupport" = "1"
-	register "SataMode" = "Sata_AHCI"
+	register "SataMode" = "SATA_AHCI"
 	register "SataPortsEnable[0]" = "1"
 	register "SataPortsEnable[1]" = "1"
 	register "SataPortsEnable[2]" = "1"
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
index c39bccf249..571a33637b 100644
--- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
+++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
@@ -172,7 +172,7 @@ chip soc/intel/cannonlake
 		device pci 16.4 off end # Management Engine Interface 3
 		device pci 16.5 off end # Management Engine Interface 4
 		device pci 17.0 on	# SATA
-			register "SataMode" = "Sata_AHCI"
+			register "SataMode" = "SATA_AHCI"
 			register "SataPortsEnable[0]" = "1" # 2.5"
 			register "SataPortsEnable[2]" = "1" # m.2
 			register "satapwroptimize" = "1"
diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb
index 8e45ebaaa8..1f92fec802 100644
--- a/src/mainboard/system76/lemp9/devicetree.cb
+++ b/src/mainboard/system76/lemp9/devicetree.cb
@@ -113,7 +113,7 @@ chip soc/intel/cannonlake
 		device pci 16.4 off end # Management Engine Interface 3
 		device pci 16.5 off end # Management Engine Interface 4
 		device pci 17.0 on	# SATA
-			register "SataMode" = "Sata_AHCI"
+			register "SataMode" = "SATA_AHCI"
 			register "SataSalpSupport" = "1"
 			# Port 2 (J_SSD2)
 			register "SataPortsEnable[1]" = "1"
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index a084f67b46..70aab92853 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -129,8 +129,8 @@ struct soc_intel_cannonlake_config {
 
 	/* SATA related */
 	enum {
-		Sata_AHCI,
-		Sata_RAID,
+		SATA_AHCI,
+		SATA_RAID,
 	} SataMode;
 
 	/* SATA devslp pad reset configuration */